Mesa (main): nir: add nir_intrinsic_load_lshs_vertex_stride_amd

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Tue Jun 7 02:12:42 UTC 2022


Module: Mesa
Branch: main
Commit: 33b4b923ee1fcc0573c82bd6fadaab6805e48ee2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=33b4b923ee1fcc0573c82bd6fadaab6805e48ee2

Author: Qiang Yu <yuq825 at gmail.com>
Date:   Sat May  7 17:34:54 2022 +0800

nir: add nir_intrinsic_load_lshs_vertex_stride_amd

For loading LS-HS vertex stride by shader argument in radeonsi.

Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Signed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>

---

 src/compiler/nir/nir_divergence_analysis.c | 1 +
 src/compiler/nir/nir_intrinsics.py         | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c
index e8f84be127b..c221841c472 100644
--- a/src/compiler/nir/nir_divergence_analysis.c
+++ b/src/compiler/nir/nir_divergence_analysis.c
@@ -176,6 +176,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
    case nir_intrinsic_load_btd_local_arg_addr_intel:
    case nir_intrinsic_load_mesh_inline_data_intel:
    case nir_intrinsic_load_ray_num_dss_rt_stacks_intel:
+   case nir_intrinsic_load_lshs_vertex_stride_amd:
       is_divergent = false;
       break;
 
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 98f84671ecc..5fc4e93fd31 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -1394,6 +1394,9 @@ intrinsic("load_shared2_amd", [1], dest_comp=2, indices=[OFFSET0, OFFSET1, ST64]
 # src[] = { value, offset }.
 intrinsic("store_shared2_amd", [2, 1], indices=[OFFSET0, OFFSET1, ST64])
 
+# Vertex stride in LS-HS buffer
+system_value("lshs_vertex_stride_amd", 1)
+
 # V3D-specific instrinc for tile buffer color reads.
 #
 # The hardware requires that we read the samples and components of a pixel



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