Mesa (main): radeonsi: implement load_lshs_vertex_stride abi

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Module: Mesa
Branch: main
Commit: 47dd3525fb2d6b342db0b9979d71e55e5e5bb4dd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=47dd3525fb2d6b342db0b9979d71e55e5e5bb4dd

Author: Qiang Yu <yuq825 at gmail.com>
Date:   Sat May  7 17:54:02 2022 +0800

radeonsi: implement load_lshs_vertex_stride abi

Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Signed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>

---

 src/amd/llvm/ac_nir_to_llvm.c                      | 1 +
 src/gallium/drivers/radeonsi/si_shader_internal.h  | 1 +
 src/gallium/drivers/radeonsi/si_shader_llvm.c      | 4 ++++
 src/gallium/drivers/radeonsi/si_shader_llvm_tess.c | 8 ++++----
 4 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 94972fd6bdf..de572aa896d 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -3643,6 +3643,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
    case nir_intrinsic_load_ring_tess_factors_amd:
    case nir_intrinsic_load_ring_tess_offchip_amd:
    case nir_intrinsic_load_ring_esgs_amd:
+   case nir_intrinsic_load_lshs_vertex_stride_amd:
       result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic);
       break;
    case nir_intrinsic_load_vertex_id:
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 12ba6c33285..d34025c529f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -244,6 +244,7 @@ void si_llvm_gs_build_end(struct si_shader_context *ctx);
 void si_llvm_init_gs_callbacks(struct si_shader_context *ctx);
 
 /* si_shader_llvm_tess.c */
+LLVMValueRef si_get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx);
 LLVMValueRef si_get_num_tcs_out_vertices(struct si_shader_context *ctx);
 void si_llvm_preload_tes_rings(struct si_shader_context *ctx);
 void si_llvm_ls_build_end(struct si_shader_context *ctx);
diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c
index 9f94403d33b..cb379d44d70 100644
--- a/src/gallium/drivers/radeonsi/si_shader_llvm.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c
@@ -772,6 +772,10 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin
    case nir_intrinsic_load_sample_mask_in:
       return ac_to_integer(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args.sample_coverage));
 
+   case nir_intrinsic_load_lshs_vertex_stride_amd:
+      return LLVMBuildShl(ctx->ac.builder, si_get_tcs_in_vertex_dw_stride(ctx),
+                          LLVMConstInt(ctx->ac.i32, 2, 0), "");
+
    default:
       return NULL;
    }
diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
index df228eed990..72c355378bb 100644
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
@@ -149,7 +149,7 @@ LLVMValueRef si_get_num_tcs_out_vertices(struct si_shader_context *ctx)
                        si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 5), ctx->ac.i32_1, "");
 }
 
-static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
+LLVMValueRef si_get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
 {
    unsigned stride;
 
@@ -419,7 +419,7 @@ static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi, LLVMType
            semantic == VARYING_SLOT_TESS_LEVEL_OUTER) == is_patch);
 
    if (load_input) {
-      stride = get_tcs_in_vertex_dw_stride(ctx);
+      stride = si_get_tcs_in_vertex_dw_stride(ctx);
       dw_addr = get_tcs_in_current_patch_offset(ctx);
    } else {
       if (is_patch) {
@@ -577,7 +577,7 @@ static void si_copy_tcs_inputs(struct si_shader_context *ctx)
    buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
    buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset);
 
-   lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
+   lds_vertex_stride = si_get_tcs_in_vertex_dw_stride(ctx);
    lds_base = get_tcs_in_current_patch_offset(ctx);
    lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride, lds_base);
 
@@ -886,7 +886,7 @@ void si_llvm_ls_build_end(struct si_shader_context *ctx)
    } else {
       vertex_id = ac_get_arg(&ctx->ac, ctx->args.vs_rel_patch_id);
    }
-   LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
+   LLVMValueRef vertex_dw_stride = si_get_tcs_in_vertex_dw_stride(ctx);
    LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id, vertex_dw_stride, "");
    LLVMValueRef *addrs = ctx->abi.outputs;
    unsigned ret_offset = 8 + GFX9_TCS_NUM_USER_SGPR + 2;