Mesa (main): radv: add few helpers related to streamout

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Thu Jun 9 08:50:09 UTC 2022


Module: Mesa
Branch: main
Commit: e0edf8d24089bc80c370933226c76a6543ca08ed
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0edf8d24089bc80c370933226c76a6543ca08ed

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Mar 29 11:24:19 2022 +0200

radv: add few helpers related to streamout

Streamout must be enabled for the PRIMITIVES_GENERATED query to work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>

---

 src/amd/vulkan/radv_cmd_buffer.c | 33 +++++++++++++++++++++++----------
 src/amd/vulkan/radv_private.h    |  3 +++
 src/amd/vulkan/radv_query.c      | 33 +++++++++++++++++----------------
 3 files changed, 43 insertions(+), 26 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 51c6bfdc1ec..056caeadd7b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6975,7 +6975,7 @@ radv_after_draw(struct radv_cmd_buffer *cmd_buffer)
    /* Workaround for a VGT hang when streamout is enabled.
     * It must be done after drawing.
     */
-   if (cmd_buffer->state.streamout.streamout_enabled &&
+   if (radv_is_streamout_enabled(cmd_buffer) &&
        (rad_info->family == CHIP_HAWAII || rad_info->family == CHIP_TONGA ||
         rad_info->family == CHIP_FIJI)) {
       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
@@ -8995,20 +8995,33 @@ radv_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t
    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
 }
 
-static void
+bool
+radv_is_streamout_enabled(struct radv_cmd_buffer *cmd_buffer)
+{
+   struct radv_streamout_state *so = &cmd_buffer->state.streamout;
+
+   return so->streamout_enabled;
+}
+
+void
 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
 {
    struct radv_streamout_state *so = &cmd_buffer->state.streamout;
    struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
-   struct radv_shader_info *info = &pipeline->streamout_shader->info;
+   bool streamout_enabled = radv_is_streamout_enabled(cmd_buffer);
    struct radeon_cmdbuf *cs = cmd_buffer->cs;
+   uint32_t enabled_stream_buffers_mask = 0;
+
+   if (pipeline && pipeline->streamout_shader) {
+      enabled_stream_buffers_mask = pipeline->streamout_shader->info.so.enabled_stream_buffers_mask;
+   }
 
    radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
-   radeon_emit(cs, S_028B94_STREAMOUT_0_EN(so->streamout_enabled) | S_028B94_RAST_STREAM(0) |
-                      S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
-                      S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
-                      S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
-   radeon_emit(cs, so->hw_enabled_mask & info->so.enabled_stream_buffers_mask);
+   radeon_emit(cs, S_028B94_STREAMOUT_0_EN(streamout_enabled) | S_028B94_RAST_STREAM(0) |
+                      S_028B94_STREAMOUT_1_EN(streamout_enabled) |
+                      S_028B94_STREAMOUT_2_EN(streamout_enabled) |
+                      S_028B94_STREAMOUT_3_EN(streamout_enabled));
+   radeon_emit(cs, so->hw_enabled_mask & enabled_stream_buffers_mask);
 
    cmd_buffer->state.context_roll_without_scissor_emitted = true;
 }
@@ -9017,7 +9030,7 @@ static void
 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
 {
    struct radv_streamout_state *so = &cmd_buffer->state.streamout;
-   bool old_streamout_enabled = so->streamout_enabled;
+   bool old_streamout_enabled = radv_is_streamout_enabled(cmd_buffer);
    uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
 
    so->streamout_enabled = enable;
@@ -9026,7 +9039,7 @@ radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
                          (so->enabled_mask << 12);
 
    if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
-       ((old_streamout_enabled != so->streamout_enabled) ||
+       ((old_streamout_enabled != radv_is_streamout_enabled(cmd_buffer)) ||
         (old_hw_enabled_mask != so->hw_enabled_mask)))
       radv_emit_streamout_enable(cmd_buffer);
 
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 52066f01863..74d0f871e66 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1600,6 +1600,9 @@ struct radv_image_view;
 
 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
 
+bool radv_is_streamout_enabled(struct radv_cmd_buffer *cmd_buffer);
+void radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer);
+
 void si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs);
 void si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs);
 
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 5a6030b84c1..3306fa4f7db 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1426,6 +1426,21 @@ event_type_for_stream(unsigned stream)
    }
 }
 
+static void
+emit_sample_streamout(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint32_t index)
+{
+   struct radeon_cmdbuf *cs = cmd_buffer->cs;
+
+   radeon_check_space(cmd_buffer->device->ws, cs, 4);
+
+   assert(index < MAX_SO_STREAMS);
+
+   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
+   radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+}
+
 static void
 emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, uint64_t va,
                  VkQueryType query_type, VkQueryControlFlags flags, uint32_t index)
@@ -1517,14 +1532,7 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo
       }
       break;
    case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
-      radeon_check_space(cmd_buffer->device->ws, cs, 4);
-
-      assert(index < MAX_SO_STREAMS);
-
-      radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
-      radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));
-      radeon_emit(cs, va);
-      radeon_emit(cs, va >> 32);
+      emit_sample_streamout(cmd_buffer, va, index);
       break;
    default:
       unreachable("beginning unhandled query type");
@@ -1599,14 +1607,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool,
       }
       break;
    case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
-      radeon_check_space(cmd_buffer->device->ws, cs, 4);
-
-      assert(index < MAX_SO_STREAMS);
-
-      radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
-      radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));
-      radeon_emit(cs, (va + 16));
-      radeon_emit(cs, (va + 16) >> 32);
+      emit_sample_streamout(cmd_buffer, va + 16, index);
       break;
    default:
       unreachable("ending unhandled query type");



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