Mesa (main): radeonsi/gfx11: add missing register shadowing code

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Module: Mesa
Branch: main
Commit: 44e4d42c23891b0cb16949fe7100555df170bab7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=44e4d42c23891b0cb16949fe7100555df170bab7

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Jun  3 17:06:57 2022 -0400

radeonsi/gfx11: add missing register shadowing code

it doesn't work yet

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16990>

---

 src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c | 43 ++++++++++++++++++++--
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
index 71b83d3223c..2ce33e06b8b 100644
--- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
+++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
@@ -90,7 +90,39 @@ si_create_shadowing_ib_preamble(struct si_context *sctx)
    si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0));
    si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
 
-   if (sctx->gfx_level >= GFX10) {
+   if (sctx->gfx_level >= GFX11) {
+      /* We must wait for idle using an EOP event before changing the attribute ring registers.
+       * Use the bottom-of-pipe EOP event, but increment the PWS counter instead of writing memory.
+       */
+      si_pm4_cmd_add(pm4, PKT3(PKT3_RELEASE_MEM, 6, 0));
+      si_pm4_cmd_add(pm4, S_490_EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) |
+                          S_490_EVENT_INDEX(5) |
+                          S_490_PWS_ENABLE(1));
+      si_pm4_cmd_add(pm4, 0); /* DST_SEL, INT_SEL, DATA_SEL */
+      si_pm4_cmd_add(pm4, 0); /* ADDRESS_LO */
+      si_pm4_cmd_add(pm4, 0); /* ADDRESS_HI */
+      si_pm4_cmd_add(pm4, 0); /* DATA_LO */
+      si_pm4_cmd_add(pm4, 0); /* DATA_HI */
+      si_pm4_cmd_add(pm4, 0); /* INT_CTXID */
+
+      unsigned gcr_cntl = S_586_GL2_INV(1) | S_586_GL2_WB(1) |
+                          S_586_GLM_INV(1) | S_586_GLM_WB(1) |
+                          S_586_GL1_INV(1) | S_586_GLV_INV(1) |
+                          S_586_GLK_INV(1) | S_586_GLI_INV(V_586_GLI_ALL);
+
+      /* Wait for the PWS counter. */
+      si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
+      si_pm4_cmd_add(pm4, S_580_PWS_STAGE_SEL(V_580_CP_PFP) |
+                          S_580_PWS_COUNTER_SEL(V_580_TS_SELECT) |
+                          S_580_PWS_ENA2(1) |
+                          S_580_PWS_COUNT(0));
+      si_pm4_cmd_add(pm4, 0xffffffff); /* GCR_SIZE */
+      si_pm4_cmd_add(pm4, 0x01ffffff); /* GCR_SIZE_HI */
+      si_pm4_cmd_add(pm4, 0); /* GCR_BASE_LO */
+      si_pm4_cmd_add(pm4, 0); /* GCR_BASE_HI */
+      si_pm4_cmd_add(pm4, S_585_PWS_ENA(1));
+      si_pm4_cmd_add(pm4, gcr_cntl); /* GCR_CNTL */
+   } else if (sctx->gfx_level >= GFX10) {
       unsigned gcr_cntl = S_586_GL2_INV(1) | S_586_GL2_WB(1) |
                           S_586_GLM_INV(1) | S_586_GLM_WB(1) |
                           S_586_GL1_INV(1) | S_586_GLV_INV(1) |
@@ -104,6 +136,9 @@ si_create_shadowing_ib_preamble(struct si_context *sctx)
       si_pm4_cmd_add(pm4, 0);		/* CP_COHER_BASE_HI */
       si_pm4_cmd_add(pm4, 0x0000000A);  /* POLL_INTERVAL */
       si_pm4_cmd_add(pm4, gcr_cntl);	/* GCR_CNTL */
+
+      si_pm4_cmd_add(pm4, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+      si_pm4_cmd_add(pm4, 0);
    } else if (sctx->gfx_level == GFX9) {
       unsigned cp_coher_cntl = S_0301F0_SH_ICACHE_ACTION_ENA(1) |
                                S_0301F0_SH_KCACHE_ACTION_ENA(1) |
@@ -118,13 +153,13 @@ si_create_shadowing_ib_preamble(struct si_context *sctx)
       si_pm4_cmd_add(pm4, 0);		  /* CP_COHER_BASE */
       si_pm4_cmd_add(pm4, 0);		  /* CP_COHER_BASE_HI */
       si_pm4_cmd_add(pm4, 0x0000000A);    /* POLL_INTERVAL */
+
+      si_pm4_cmd_add(pm4, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+      si_pm4_cmd_add(pm4, 0);
    } else {
       unreachable("invalid chip");
    }
 
-   si_pm4_cmd_add(pm4, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
-   si_pm4_cmd_add(pm4, 0);
-
    si_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
    si_pm4_cmd_add(pm4,
                   CC0_UPDATE_LOAD_ENABLES(1) |