Mesa (main): dzn: Disable rasterization if the last geometry stage doesn't write the position

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Wed Jun 15 22:47:33 UTC 2022


Module: Mesa
Branch: main
Commit: e9066ff2be33c5cb147185374f4c92a2902c2f77
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9066ff2be33c5cb147185374f4c92a2902c2f77

Author: Boris Brezillon <boris.brezillon at collabora.com>
Date:   Tue Jun 14 22:27:32 2022 +0200

dzn: Disable rasterization if the last geometry stage doesn't write the position

If we don't do that, and we get passed a dummy geometry shader (one
that has no EmitVertex() calls) we get a DXIL validation error.

Reviewed-by: Jesse Natalie <jenatali at microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17039>

---

 src/microsoft/vulkan/dzn_pipeline.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/microsoft/vulkan/dzn_pipeline.c b/src/microsoft/vulkan/dzn_pipeline.c
index a66a3eeb243..6eab6abe13f 100644
--- a/src/microsoft/vulkan/dzn_pipeline.c
+++ b/src/microsoft/vulkan/dzn_pipeline.c
@@ -422,6 +422,17 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
 
    /* Last step: translate NIR shaders into DXIL modules */
    u_foreach_bit(stage, active_stage_mask) {
+      if (stage == MESA_SHADER_FRAGMENT) {
+         gl_shader_stage prev_stage =
+            util_last_bit(active_stage_mask & BITFIELD_MASK(MESA_SHADER_FRAGMENT)) - 1;
+         /* Disable rasterization if the last geometry stage doesn't
+	  * write the position.
+	  */
+	 if (prev_stage == MESA_SHADER_NONE ||
+             !(stages[prev_stage].nir->info.outputs_written & VARYING_BIT_POS))
+            continue;
+      }
+
       D3D12_SHADER_BYTECODE *slot =
          dzn_pipeline_get_gfx_shader_slot(out, stage);
 



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