Mesa (main): nir/lower_task_shader: don't use base index for shared memory intrinsics
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Wed Jun 22 11:27:36 UTC 2022
Module: Mesa
Branch: main
Commit: e5970fe22a66bf1727d8b677f4e3c93fe2172a71
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5970fe22a66bf1727d8b677f4e3c93fe2172a71
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Mon Jun 20 17:31:06 2022 +0200
nir/lower_task_shader: don't use base index for shared memory intrinsics
Intel backend doesn't handle them very well.
Fixes: 8aff8d3dd42 ("nir: Add common task shader lowering to make the backend's job easier.")
Reviewed-by: Marcin Ślusarz <marcin.slusarz at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17143>
---
src/compiler/nir/nir_lower_task_shader.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/compiler/nir/nir_lower_task_shader.c b/src/compiler/nir/nir_lower_task_shader.c
index 6d7040828fe..1417cbdea44 100644
--- a/src/compiler/nir/nir_lower_task_shader.c
+++ b/src/compiler/nir/nir_lower_task_shader.c
@@ -55,8 +55,7 @@ lower_nv_task_output(nir_builder *b,
case nir_intrinsic_load_output: {
b->cursor = nir_after_instr(instr);
nir_ssa_def *load =
- nir_load_shared(b, 1, 32, nir_imm_int(b, 0),
- .base = s->task_count_shared_addr);
+ nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr));
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load);
nir_instr_remove(instr);
return true;
@@ -65,8 +64,7 @@ lower_nv_task_output(nir_builder *b,
case nir_intrinsic_store_output: {
b->cursor = nir_after_instr(instr);
nir_ssa_def *store_val = intrin->src[0].ssa;
- nir_store_shared(b, store_val, nir_imm_int(b, 0),
- .base = s->task_count_shared_addr);
+ nir_store_shared(b, store_val, nir_imm_int(b, s->task_count_shared_addr));
nir_instr_remove(instr);
return true;
}
@@ -86,7 +84,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b,
*/
b->cursor = nir_before_cf_list(&b->impl->body);
nir_ssa_def *zero = nir_imm_int(b, 0);
- nir_store_shared(b, zero, zero, .base = s->task_count_shared_addr);
+ nir_store_shared(b, zero, nir_imm_int(b, s->task_count_shared_addr));
nir_scoped_barrier(b,
.execution_scope = NIR_SCOPE_WORKGROUP,
@@ -106,7 +104,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b,
.memory_modes = nir_var_mem_shared);
nir_ssa_def *task_count =
- nir_load_shared(b, 1, 32, zero, .base = s->task_count_shared_addr);
+ nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr));
/* NV_mesh_shader doesn't offer to choose which task_payload variable
* should be passed to mesh shaders, we just pass all.
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