Mesa (main): nir: i32csel opcodes should compare with integer zero

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Module: Mesa
Branch: main
Commit: ccd18ec4f34b6f1407fb7c1671de8c789f33fa1f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccd18ec4f34b6f1407fb7c1671de8c789f33fa1f

Author: Ian Romanick <ian.d.romanick at intel.com>
Date:   Wed Jun 15 09:21:10 2022 -0700

nir: i32csel opcodes should compare with integer zero

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa at collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Noticed-by: Georg Lehmann <dadschoorse at gmail.com>
Fixes: 0f5b3c37c5d ("nir: Add opcodes for fused comp + csel and optimizations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17048>

---

 src/compiler/nir/nir_opcodes.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index a9fee18c361..dd8959e9523 100644
--- a/src/compiler/nir/nir_opcodes.py
+++ b/src/compiler/nir/nir_opcodes.py
@@ -1019,8 +1019,8 @@ opcode("b16csel", 0, tuint, [0, 0, 0],
 opcode("b32csel", 0, tuint, [0, 0, 0],
        [tbool32, tuint, tuint], False, "", "src0 ? src1 : src2")
 
-triop("i32csel_gt", tint32, "", "(src0 > 0.0f) ? src1 : src2")
-triop("i32csel_ge", tint32, "", "(src0 >= 0.0f) ? src1 : src2")
+triop("i32csel_gt", tint32, "", "(src0 > 0) ? src1 : src2")
+triop("i32csel_ge", tint32, "", "(src0 >= 0) ? src1 : src2")
 
 triop("fcsel_gt", tfloat32, "", "(src0 > 0.0f) ? src1 : src2")
 triop("fcsel_ge", tfloat32, "", "(src0 >= 0.0f) ? src1 : src2")