Mesa (main): anv: limit RT writes to number of color outputs
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gitlab-mirror at kemper.freedesktop.org
Wed Jun 22 22:22:02 UTC 2022
Module: Mesa
Branch: main
Commit: 5d05ffa465329ac0d804510e9882c245f9a12ee1
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d05ffa465329ac0d804510e9882c245f9a12ee1
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Apr 4 23:40:24 2022 +0300
anv: limit RT writes to number of color outputs
Not doing so crates skews occlusion queries. Fixes Zink's piglit
occlusion_query tests.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: a4f502de3228 ("anv: fix VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6205
Reviewed-by: Emma Anholt <emma at anholt.net>
Reviewed-by: Ivan Briano <ivan.briano at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15740>
---
src/intel/vulkan/anv_pipeline.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 9f2c78284db..5ebac29bb1d 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -486,8 +486,8 @@ populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
assert(rendering_info->colorAttachmentCount <= MAX_RTS);
/* Consider all inputs as valid until look at the NIR variables. */
- key->color_outputs_valid = (1u << MAX_RTS) - 1;
- key->nr_color_regions = MAX_RTS;
+ key->color_outputs_valid = (1u << rendering_info->colorAttachmentCount) - 1;
+ key->nr_color_regions = rendering_info->colorAttachmentCount;
/* To reduce possible shader recompilations we would need to know if
* there is a SampleMask output variable to compute if we should emit
@@ -1125,7 +1125,8 @@ anv_pipeline_compile_mesh(const struct brw_compiler *compiler,
static void
anv_pipeline_link_fs(const struct brw_compiler *compiler,
- struct anv_pipeline_stage *stage)
+ struct anv_pipeline_stage *stage,
+ const VkPipelineRenderingCreateInfo *rendering_info)
{
/* Initially the valid outputs value is set to all possible render targets
* valid (see populate_wm_prog_key()), before we look at the shader
@@ -1144,6 +1145,8 @@ anv_pipeline_link_fs(const struct brw_compiler *compiler,
stage->key.wm.color_outputs_valid |= BITFIELD_RANGE(rt, array_len);
}
+ stage->key.wm.color_outputs_valid &=
+ (1u << rendering_info->colorAttachmentCount) - 1;
stage->key.wm.nr_color_regions =
util_last_bit(stage->key.wm.color_outputs_valid);
@@ -1682,7 +1685,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
anv_pipeline_link_mesh(compiler, &stages[s], next_stage);
break;
case MESA_SHADER_FRAGMENT:
- anv_pipeline_link_fs(compiler, &stages[s]);
+ anv_pipeline_link_fs(compiler, &stages[s], rendering_info);
break;
default:
unreachable("Invalid graphics shader stage");
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