Mesa (staging/22.1): broadcom/compiler: don't predicate postponed spills

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Module: Mesa
Branch: staging/22.1
Commit: d11aac344356525a16af882d856d9b578bb6c002
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d11aac344356525a16af882d856d9b578bb6c002

Author: Iago Toral Quiroga <itoral at igalia.com>
Date:   Wed Jun 22 09:43:30 2022 +0200

broadcom/compiler: don't predicate postponed spills

The postponed spill is predicated using the condition from the
last write, but this is only correct if the register was only
written once in the TMU sequence, or if it is always written with
the same predication.

While we could try to track whether this is the case or not, it
would make the postponed spill path even more complex than it
already is, so let's just avoid predicating these. We are already
discouraging TMU spilling of registers in the middle of TMU
sequences, so this should not be a very common case.

Cc: mesa-stable
Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17201>
(cherry picked from commit cfccd93efc95277a739a202a036cbea36fde85f4)

---

 .pick_status.json                             |  2 +-
 src/broadcom/compiler/vir_register_allocate.c | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 34547cbb59b..fb1850b079f 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -463,7 +463,7 @@
         "description": "broadcom/compiler: don't predicate postponed spills",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c
index 09107523fb1..ca1428bdfb6 100644
--- a/src/broadcom/compiler/vir_register_allocate.c
+++ b/src/broadcom/compiler/vir_register_allocate.c
@@ -499,6 +499,8 @@ v3d_emit_tmu_spill(struct v3d_compile *c,
 
         c->cursor = vir_after_inst(position);
 
+        enum v3d_qpu_cond cond = vir_get_cond(inst);
+
         /* If inst and position don't match, this is a postponed spill,
          * in which case we have already allocated the temp for the spill
          * and we should use that, otherwise create a new temp with the
@@ -511,9 +513,15 @@ v3d_emit_tmu_spill(struct v3d_compile *c,
                 add_node(c, inst->dst.index, class_bits);
         } else {
                 inst->dst = spill_temp;
+
+                /* If this is a postponed spill the register being spilled may
+                 * have been written more than once including conditional
+                 * writes, so ignore predication on the spill instruction and
+                 * always spill the full register.
+                 */
+                cond = V3D_QPU_COND_NONE;
         }
 
-        enum v3d_qpu_cond cond = vir_get_cond(inst);
         struct qinst *tmp =
                 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
                              inst->dst);