Mesa (main): freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE

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Module: Mesa
Branch: main
Commit: 6cb41c51884c2488194f74e2ce637b950c835620
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cb41c51884c2488194f74e2ce637b950c835620

Author: Hyunjun Ko <zzoon at igalia.com>
Date:   Tue Jun 28 14:11:15 2022 +0900

freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE

UNK5 of GRAS_CL_CNTL is still unclear though.

Signed-off-by: Hyunjun Ko <zzoon at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

---

 src/freedreno/registers/adreno/a6xx.xml         | 2 +-
 src/freedreno/vulkan/tu_pipeline.c              | 2 +-
 src/gallium/drivers/freedreno/a6xx/fd6_emit.c   | 8 ++++----
 src/gallium/drivers/freedreno/a6xx/fd6_zsa.c    | 4 ++--
 src/gallium/drivers/freedreno/a6xx/fd6_zsa.h    | 4 ++--
 src/gallium/drivers/freedreno/freedreno_state.h | 2 +-
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index b5a1a810e36..b1b1d926d9b 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2128,7 +2128,7 @@ to upconvert to 32b float internally?
 		<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
 		<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
 		<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
-		<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
+		<bitfield name="Z_CLIP_DISABLE" pos="5" type="boolean"/>
 		<doc>
 		Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
 		also set when Z_BOUNDS_ENABLE is set
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 62f502c0234..3cb1fa091c0 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -3466,7 +3466,7 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
             A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
 
          if (rast_info->depthClampEnable)
-            rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
+            rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLIP_DISABLE;
 
          if (ds_info->depthWriteEnable)
             rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index b59dd5f598f..bb2249aad7f 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -983,11 +983,11 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
                                                     .vert = guardband_y));
    }
 
-   /* The clamp ranges are only used when the rasterizer wants depth
-    * clamping.
+   /* The clamp ranges are only used when the rasterizer disables
+    * depth clip.
     */
    if ((dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER)) &&
-       fd_depth_clamp_enabled(ctx)) {
+       fd_depth_clip_disabled(ctx)) {
       float zmin, zmax;
       util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
                               &zmin, &zmax);
@@ -1037,7 +1037,7 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
          state = fd6_zsa_state(
             ctx,
             util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])),
-            fd_depth_clamp_enabled(ctx));
+            fd_depth_clip_disabled(ctx));
          fd_ringbuffer_ref(state);
          break;
       case FD6_GROUP_LRZ:
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
index 5c8bf5e4050..cc06b344e65 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
@@ -215,8 +215,8 @@ fd6_zsa_state_create(struct pipe_context *pctx,
 
       OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
       OUT_RING(ring,
-               so->rb_depth_cntl | COND(i & FD6_ZSA_DEPTH_CLAMP,
-                                        A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE));
+               so->rb_depth_cntl | COND(i & FD6_ZSA_DEPTH_CLIP_DISABLE,
+                                        A6XX_RB_DEPTH_CNTL_Z_CLIP_DISABLE));
 
       OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
       OUT_RING(ring, so->rb_stencilmask);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
index 15be91e1bfe..aa0baa7a5c7 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
@@ -36,7 +36,7 @@
 #include "fd6_context.h"
 
 #define FD6_ZSA_NO_ALPHA    (1 << 0)
-#define FD6_ZSA_DEPTH_CLAMP (1 << 1)
+#define FD6_ZSA_DEPTH_CLIP_DISABLE (1 << 1)
 
 struct fd6_zsa_stateobj {
    struct pipe_depth_stencil_alpha_state base;
@@ -68,7 +68,7 @@ fd6_zsa_state(struct fd_context *ctx, bool no_alpha, bool depth_clamp) assert_dt
    if (no_alpha)
       variant |= FD6_ZSA_NO_ALPHA;
    if (depth_clamp)
-      variant |= FD6_ZSA_DEPTH_CLAMP;
+      variant |= FD6_ZSA_DEPTH_CLIP_DISABLE;
    return fd6_zsa_stateobj(ctx->zsa)->stateobj[variant];
 }
 
diff --git a/src/gallium/drivers/freedreno/freedreno_state.h b/src/gallium/drivers/freedreno/freedreno_state.h
index 1890583b5a2..4917ecf9a74 100644
--- a/src/gallium/drivers/freedreno/freedreno_state.h
+++ b/src/gallium/drivers/freedreno/freedreno_state.h
@@ -55,7 +55,7 @@ fd_blend_enabled(struct fd_context *ctx, unsigned n) assert_dt
 }
 
 static inline bool
-fd_depth_clamp_enabled(struct fd_context *ctx) assert_dt
+fd_depth_clip_disabled(struct fd_context *ctx) assert_dt
 {
    return !(ctx->rasterizer->depth_clip_near &&
             ctx->rasterizer->depth_clip_far);