Mesa (main): panvk: Emit fragment RSDs even with no shader

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Module: Mesa
Branch: main
Commit: 7864f653ad480316d9b2966d843fa6b49ee110ec
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7864f653ad480316d9b2966d843fa6b49ee110ec

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed Apr 27 18:57:04 2022 -0400

panvk: Emit fragment RSDs even with no shader

In Vulkan, it's possible to create a pipeline with no fragment shader that's
still expected to rasterize. This is useful for depth/stencil side effects, and
is closely related to the "fragment shader required" optimization we do in the
GLES driver. Refactor the RSD emit code to handle this case.

Fixes dEQP-VK.pipeline.stencil.nocolor.*

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>

---

 src/panfrost/ci/deqp-panfrost-g52-vk.toml |  1 +
 src/panfrost/vulkan/panvk_vX_pipeline.c   | 45 +++++++++++++++++--------------
 2 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/panfrost/ci/deqp-panfrost-g52-vk.toml b/src/panfrost/ci/deqp-panfrost-g52-vk.toml
index a0775789ce9..54b60d7725c 100644
--- a/src/panfrost/ci/deqp-panfrost-g52-vk.toml
+++ b/src/panfrost/ci/deqp-panfrost-g52-vk.toml
@@ -25,6 +25,7 @@ include = [
     "dEQP-VK.image.load_store.with_format.*",
     "dEQP-VK.pipeline.input_assembly.*",
     "dEQP-VK.pipeline.sampler.view_type.*.format.r*.address_modes.all_mode_clamp_to_border*",
+    "dEQP-VK.pipeline.stencil.*",
     "dEQP-VK.rasterization.interpolation.*",
     "dEQP-VK.rasterization.primitive_size.*",
     "dEQP-VK.spirv_assembly.instruction.compute.opquantize.*",
diff --git a/src/panfrost/vulkan/panvk_vX_pipeline.c b/src/panfrost/vulkan/panvk_vX_pipeline.c
index 753546d1d2a..c7178d7a9da 100644
--- a/src/panfrost/vulkan/panvk_vX_pipeline.c
+++ b/src/panfrost/vulkan/panvk_vX_pipeline.c
@@ -212,7 +212,7 @@ panvk_pipeline_builder_alloc_static_state_bo(struct panvk_pipeline_builder *buil
 
    for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
       const struct panvk_shader *shader = builder->shaders[i];
-      if (!shader)
+      if (!shader && i != MESA_SHADER_FRAGMENT)
          continue;
 
       if (pipeline->fs.dynamic_rsd && i == MESA_SHADER_FRAGMENT)
@@ -358,35 +358,40 @@ panvk_pipeline_builder_init_shaders(struct panvk_pipeline_builder *builder,
                       builder->stages[i].shader_offset;
       }
 
-      void *rsd = pipeline->state_bo->ptr.cpu + builder->stages[i].rsd_offset;
-      mali_ptr gpu_rsd = pipeline->state_bo->ptr.gpu + builder->stages[i].rsd_offset;
-
       if (i != MESA_SHADER_FRAGMENT) {
-         panvk_per_arch(emit_non_fs_rsd)(builder->device, &shader->info, shader_ptr, rsd);
-      } else if (!pipeline->fs.dynamic_rsd) {
-         void *bd = rsd + pan_size(RENDERER_STATE);
+         void *rsd = pipeline->state_bo->ptr.cpu + builder->stages[i].rsd_offset;
+         mali_ptr gpu_rsd = pipeline->state_bo->ptr.gpu + builder->stages[i].rsd_offset;
 
-         panvk_per_arch(emit_base_fs_rsd)(builder->device, pipeline, rsd);
-         for (unsigned rt = 0; rt < MAX2(pipeline->blend.state.rt_count, 1); rt++) {
-            panvk_per_arch(emit_blend)(builder->device, pipeline, rt, bd);
-            bd += pan_size(BLEND);
-         }
-      } else {
-         gpu_rsd = 0;
-         panvk_per_arch(emit_base_fs_rsd)(builder->device, pipeline, &pipeline->fs.rsd_template);
-         for (unsigned rt = 0; rt < MAX2(pipeline->blend.state.rt_count, 1); rt++) {
-            panvk_per_arch(emit_blend)(builder->device, pipeline, rt,
-                                       &pipeline->blend.bd_template[rt]);
-         }
+         panvk_per_arch(emit_non_fs_rsd)(builder->device, &shader->info, shader_ptr, rsd);
+         pipeline->rsds[i] = gpu_rsd;
       }
 
-      pipeline->rsds[i] = gpu_rsd;
       panvk_pipeline_builder_init_sysvals(builder, pipeline, i);
 
       if (i == MESA_SHADER_COMPUTE)
          pipeline->cs.local_size = shader->local_size;
    }
 
+   if (builder->create_info.gfx && !pipeline->fs.dynamic_rsd) {
+      void *rsd = pipeline->state_bo->ptr.cpu + builder->stages[MESA_SHADER_FRAGMENT].rsd_offset;
+      mali_ptr gpu_rsd = pipeline->state_bo->ptr.gpu + builder->stages[MESA_SHADER_FRAGMENT].rsd_offset;
+      void *bd = rsd + pan_size(RENDERER_STATE);
+
+      panvk_per_arch(emit_base_fs_rsd)(builder->device, pipeline, rsd);
+      for (unsigned rt = 0; rt < pipeline->blend.state.rt_count; rt++) {
+         panvk_per_arch(emit_blend)(builder->device, pipeline, rt, bd);
+         bd += pan_size(BLEND);
+      }
+
+      pipeline->rsds[MESA_SHADER_FRAGMENT] = gpu_rsd;
+   } else if (builder->create_info.gfx) {
+      panvk_per_arch(emit_base_fs_rsd)(builder->device, pipeline, &pipeline->fs.rsd_template);
+      for (unsigned rt = 0; rt < MAX2(pipeline->blend.state.rt_count, 1); rt++) {
+         panvk_per_arch(emit_blend)(builder->device, pipeline, rt,
+                                    &pipeline->blend.bd_template[rt]);
+      }
+   }
+
    pipeline->num_ubos = builder->layout->num_ubos + builder->layout->num_dyn_ubos;
    for (unsigned i = 0; i < ARRAY_SIZE(pipeline->sysvals); i++) {
       if (pipeline->sysvals[i].ids.sysval_count)