Mesa (main): pan/bi: Align spilled registers on Valhall

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Module: Mesa
Branch: main
Commit: 961b18ccbca0a7e6c85a4851a7cd6ffdcfeba0dd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=961b18ccbca0a7e6c85a4851a7cd6ffdcfeba0dd

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Tue May  3 17:01:24 2022 -0400

pan/bi: Align spilled registers on Valhall

Required to support packed addressing correctly. Fixes (with spilling forced):

dEQP-GLES2.functional.shaders.random.trigonometric.vertex.20

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16314>

---

 src/panfrost/bifrost/bi_ra.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c
index 8b14c0ec79a..8a7fa6309d9 100644
--- a/src/panfrost/bifrost/bi_ra.c
+++ b/src/panfrost/bifrost/bi_ra.c
@@ -591,6 +591,14 @@ bi_register_allocate(bi_context *ctx)
                         if (spill_node == -1)
                                 unreachable("Failed to choose spill node\n");
 
+                        /* By default, we use packed TLS addressing on Valhall.
+                         * We cannot cross 16 byte boundaries with packed TLS
+                         * addressing. Align to ensure this doesn't happen. This
+                         * could be optimized a bit.
+                         */
+                        if (ctx->arch >= 9)
+                                spill_count = ALIGN_POT(spill_count, 16);
+
                         spill_count += bi_spill_register(ctx,
                                         bi_node_to_index(spill_node, bi_max_temp(ctx)),
                                         spill_count);