Mesa (staging/22.1): anv: don't emit 3DSTATE_WM in pipeline batch

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Module: Mesa
Branch: staging/22.1
Commit: 265351f03fe5f403d6a68cfe7fda2ac3080c551e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=265351f03fe5f403d6a68cfe7fda2ac3080c551e

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Thu Apr 28 09:26:39 2022 +0300

anv: don't emit 3DSTATE_WM in pipeline batch

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit e9d000a831c767f93c9e22087eb92ce4db044935)

---

 .pick_status.json                  |  2 +-
 src/intel/vulkan/genX_pipeline.c   | 17 +++--------------
 src/intel/vulkan/gfx7_cmd_buffer.c |  5 +++--
 src/intel/vulkan/gfx8_cmd_buffer.c | 13 +++++++++----
 4 files changed, 16 insertions(+), 21 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index bf7f536a493..762f7442bdd 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -958,7 +958,7 @@
         "description": "anv: don't emit 3DSTATE_WM in pipeline batch",
         "nominated": false,
         "nomination_type": null,
-        "resolution": 4,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 1bb03d34ab7..9471590a85d 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -2334,20 +2334,9 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
       wm.LineStippleEnable = line && line->stippledLineEnable;
    }
 
-   uint32_t dynamic_wm_states = ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE;
-
-#if GFX_VER < 8
-   dynamic_wm_states |= ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
-#endif
-
-   if (dynamic_states & dynamic_wm_states) {
-      const struct intel_device_info *devinfo = &pipeline->base.device->info;
-      uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm;
-      GENX(3DSTATE_WM_pack)(NULL, dws, &wm);
-   } else {
-      anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_WM), _wm)
-         _wm = wm;
-   }
+   const struct intel_device_info *devinfo = &pipeline->base.device->info;
+   uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm;
+   GENX(3DSTATE_WM_pack)(NULL, dws, &wm);
 }
 
 static void
diff --git a/src/intel/vulkan/gfx7_cmd_buffer.c b/src/intel/vulkan/gfx7_cmd_buffer.c
index 6f9d619fc77..524b84a8200 100644
--- a/src/intel/vulkan/gfx7_cmd_buffer.c
+++ b/src/intel/vulkan/gfx7_cmd_buffer.c
@@ -290,8 +290,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       struct GENX(3DSTATE_WM) wm = {
          GENX(3DSTATE_WM_header),
 
-         .ThreadDispatchEnable = pipeline->force_fragment_thread_dispatch ||
-                                 !anv_cmd_buffer_all_color_write_masked(cmd_buffer),
+         .ThreadDispatchEnable = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
+                                 (pipeline->force_fragment_thread_dispatch ||
+                                  !anv_cmd_buffer_all_color_write_masked(cmd_buffer)),
          .MultisampleRasterizationMode =
                                  genX(ms_rasterization_mode)(pipeline,
                                                              dynamic_raster_mode),
diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index 7d100cf120d..33189cc85bb 100644
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -628,9 +628,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       genX(emit_sample_pattern)(&cmd_buffer->batch, d);
 
    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
-                                      ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
-                                      ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
-      const uint8_t color_writes = d->color_writes;
+                                      ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
       /* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
        * threads.
        */
@@ -638,13 +636,20 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       struct GENX(3DSTATE_WM) wm = {
          GENX(3DSTATE_WM_header),
 
-         .ForceThreadDispatchEnable = (pipeline->force_fragment_thread_dispatch ||
+         .ForceThreadDispatchEnable = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
+                                      (pipeline->force_fragment_thread_dispatch ||
                                        anv_cmd_buffer_all_color_write_masked(cmd_buffer)) ?
                                       ForceON : 0,
       };
       GENX(3DSTATE_WM_pack)(NULL, wm_dwords, &wm);
 
       anv_batch_emit_merge(&cmd_buffer->batch, wm_dwords, pipeline->gfx8.wm);
+   }
+
+   if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
+                                      ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
+                                      ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
+      const uint8_t color_writes = d->color_writes;
 
       /* 3DSTATE_PS_BLEND to be consistent with the rest of the
        * BLEND_STATE_ENTRY.