Mesa (main): radv: Refactor cache flush code for the initial preambles.

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Module: Mesa
Branch: main
Commit: 86821329c705c9fd7c323c53f8ad3f2e40081302
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=86821329c705c9fd7c323c53f8ad3f2e40081302

Author: Timur Kristóf <timur.kristof at gmail.com>
Date:   Thu May  5 20:04:46 2022 +0200

radv: Refactor cache flush code for the initial preambles.

The "initial" and "initial full flush" preambles both need a
cache flush with a slight difference. Improve the readability of
this code.

Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>

---

 src/amd/vulkan/radv_device.c | 35 ++++++++++++++++-------------------
 1 file changed, 16 insertions(+), 19 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 259894ece11..dc9f00868b9 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4177,25 +4177,22 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave,
       if (gds_oa_bo)
          radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
 
-      if (i == 0) {
-         si_cs_emit_cache_flush(
-            cs, queue->device->physical_device->rad_info.chip_class, NULL, 0,
-            queue->qf == RADV_QUEUE_COMPUTE &&
-               queue->device->physical_device->rad_info.chip_class >= GFX7,
-            (queue->qf == RADV_QUEUE_COMPUTE
-                ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
-                : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
-               RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SCACHE | RADV_CMD_FLAG_INV_VCACHE |
-               RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_START_PIPELINE_STATS,
-            &sqtt_flush_bits, 0);
-      } else if (i == 1) {
-         si_cs_emit_cache_flush(cs, queue->device->physical_device->rad_info.chip_class, NULL, 0,
-                                queue->qf == RADV_QUEUE_COMPUTE &&
-                                   queue->device->physical_device->rad_info.chip_class >= GFX7,
-                                RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SCACHE |
-                                   RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2 |
-                                   RADV_CMD_FLAG_START_PIPELINE_STATS,
-                                &sqtt_flush_bits, 0);
+      if (i < 2) {
+         /* The two initial preambles have a cache flush at the beginning. */
+         const enum chip_class chip_class = queue->device->physical_device->rad_info.chip_class;
+         const bool is_mec = queue->qf == RADV_QUEUE_COMPUTE && chip_class >= GFX7;
+         enum radv_cmd_flush_bits flush_bits = RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SCACHE |
+                                               RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2 |
+                                               RADV_CMD_FLAG_START_PIPELINE_STATS;
+
+         if (i == 0) {
+            /* The full flush preamble should also wait for previous shader work to finish. */
+            flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
+            if (queue->qf == RADV_QUEUE_GENERAL)
+               flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
+         }
+
+         si_cs_emit_cache_flush(cs, chip_class, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0);
       }
 
       result = queue->device->ws->cs_finalize(cs);