Mesa (main): nir: Add upper bound for AMD shader arg intrinsics.

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Module: Mesa
Branch: main
Commit: 7f189e346731f16e8be2d969d22d83dba917dca6
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f189e346731f16e8be2d969d22d83dba917dca6

Author: Timur Kristóf <timur.kristof at gmail.com>
Date:   Wed Mar 23 18:44:57 2022 +0100

nir: Add upper bound for AMD shader arg intrinsics.

Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>

---

 src/compiler/nir/nir_intrinsics.py    | 7 +++++--
 src/compiler/nir/nir_range_analysis.c | 7 +++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index f3b4a739054..7bf257f2f03 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -234,6 +234,9 @@ index("uint8_t", "offset1")
 # in hardware, instead of 4).
 index("bool", "st64")
 
+# When set, range analysis will use it for nir_unsigned_upper_bound
+index("unsigned", "arg_upper_bound_u32_amd")
+
 # Separate source/dest access flags for copies
 index("enum gl_access_qualifier", "dst_access")
 index("enum gl_access_qualifier", "src_access")
@@ -1346,8 +1349,8 @@ system_value("intersection_opaque_amd", 1, bit_sizes=[1])
 # Load forced VRS rates.
 intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER])
 
-intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER])
-intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER])
+intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER])
+intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER])
 
 # src[] = { 64-bit base address, 32-bit offset }.
 intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32],
diff --git a/src/compiler/nir/nir_range_analysis.c b/src/compiler/nir/nir_range_analysis.c
index 29b2903ca54..46a7dc8b469 100644
--- a/src/compiler/nir/nir_range_analysis.c
+++ b/src/compiler/nir/nir_range_analysis.c
@@ -1416,6 +1416,13 @@ nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht,
          /* Very generous maximum: TCS/TES executed by largest possible workgroup */
          res = config->max_workgroup_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u);
          break;
+      case nir_intrinsic_load_scalar_arg_amd:
+      case nir_intrinsic_load_vector_arg_amd: {
+         uint32_t upper_bound = nir_intrinsic_arg_upper_bound_u32_amd(intrin);
+         if (upper_bound)
+            res = upper_bound;
+         break;
+      }
       default:
          break;
       }