Mesa (staging/22.1): pan/mdg: Fix mask usage when filling before a spill
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gitlab-mirror at kemper.freedesktop.org
Wed May 11 04:23:24 UTC 2022
Module: Mesa
Branch: staging/22.1
Commit: 7feaf6c548f5c3bd619b910466773b5e9099fd83
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7feaf6c548f5c3bd619b910466773b5e9099fd83
Author: Icecream95 <ixn at disroot.org>
Date: Fri Dec 10 23:40:01 2021 +1300
pan/mdg: Fix mask usage when filling before a spill
Check the bytemask against 0xFFFF rather than 0xF so that the fill is
skipped for a .xyzw write rather than a .x write.
Set the mask on the store to 0xF when doing a read so that all
components are written back.
Fixes: 31d26ebf1b9 ("pan/mdg: Fill from TLS before spilling non-SSA nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
(cherry picked from commit c750ab8a389b82795bb1509250711671c19f583d)
---
.pick_status.json | 2 +-
src/panfrost/midgard/midgard_ra.c | 9 +++++++--
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 249fbae10f1..0237064317f 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -679,7 +679,7 @@
"description": "pan/mdg: Fix mask usage when filling before a spill",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": "31d26ebf1b9d0f819c894aec10c29a44052a995a"
},
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index e3922639432..dea96086948 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -946,10 +946,15 @@ mir_spill_register(
} else {
unsigned dest = spill_index++;
- if (write_count > 1 && mir_bytemask(ins) != 0xF) {
+ unsigned bytemask = mir_bytemask(ins);
+ unsigned write_mask = mir_from_bytemask(mir_round_bytemask_up(
+ bytemask, 32), 32);
+
+ if (write_count > 1 && bytemask != 0xFFFF) {
midgard_instruction read =
v_load_store_scratch(dest, spill_slot, false, 0xF);
mir_insert_instruction_before_scheduled(ctx, block, ins, read);
+ write_mask = 0xF;
}
ins->dest = dest;
@@ -977,7 +982,7 @@ mir_spill_register(
dest = spill_index++;
midgard_instruction st =
- v_load_store_scratch(dest, spill_slot, true, ins->mask);
+ v_load_store_scratch(dest, spill_slot, true, write_mask);
mir_insert_instruction_after_scheduled(ctx, block, ins, st);
if (move) {
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