Mesa (main): radv: Enable nir_opt_offsets for task shaders.

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Module: Mesa
Branch: main
Commit: 6e8f3677c7ea3d96596e86990c0fa87b99248a04
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e8f3677c7ea3d96596e86990c0fa87b99248a04

Author: Timur Kristóf <timur.kristof at gmail.com>
Date:   Tue Jan 18 16:37:53 2022 +0100

radv: Enable nir_opt_offsets for task shaders.

Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

---

 src/amd/vulkan/radv_pipeline.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7df2f58717d..4a73eccc4a3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4504,7 +4504,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
          ac_nir_lower_global_access(stages[i].nir);
          radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.chip_class,
                             &stages[i].info, &stages[i].args, pipeline_key);
-         radv_optimize_nir_algebraic(stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE);
+         radv_optimize_nir_algebraic(
+            stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE || i == MESA_SHADER_TASK);
 
          if (stages[i].nir->info.bit_sizes_int & (8 | 16)) {
             if (device->physical_device->rad_info.chip_class >= GFX8) {