Mesa (main): radeonsi: flush VGT streamout like PAL

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Module: Mesa
Branch: main
Commit: 283730f3680b0c282a070cb22c395a873abe9742
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=283730f3680b0c282a070cb22c395a873abe9742

Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date:   Mon Apr 11 16:25:01 2022 +0200

radeonsi: flush VGT streamout like PAL

Ported from 165b016bbeedd4e8d1517a5e95949871cc55a123.

Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

---

 src/gallium/drivers/radeonsi/si_state_streamout.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 0406c7d0198..baceace822f 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -283,7 +283,14 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
    radeon_begin(cs);
 
    /* The register is at different places on different ASICs. */
-   if (sctx->chip_class >= GFX7) {
+   if (sctx->chip_class >= GFX9) {
+      reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
+      radeon_emit(PKT3(PKT3_WRITE_DATA, 3, 0));
+      radeon_emit(S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME));
+      radeon_emit(R_0300FC_CP_STRMOUT_CNTL >> 2);
+      radeon_emit(0);
+      radeon_emit(0);
+   } else if (sctx->chip_class >= GFX7) {
       reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
       radeon_set_uconfig_reg(reg_strmout_cntl, 0);
    } else {