Mesa (main): radv,aco: add support for packed threadID VGPRs on GFX11

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Module: Mesa
Branch: main
Commit: 432cde7f00a6ffd7c4d8984bb0cba389824a97bc
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=432cde7f00a6ffd7c4d8984bb0cba389824a97bc

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Wed May  4 21:35:58 2022 +0200

radv,aco: add support for packed threadID VGPRs on GFX11

Thread ID are packed in one VGPR with 10 bits each.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16369>

---

 src/amd/compiler/aco_instruction_selection.cpp | 16 +++++++++++++++-
 src/amd/vulkan/radv_shader_args.c              |  5 ++++-
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 7ca337d1a72..10814cbbde5 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -8178,7 +8178,21 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
    }
    case nir_intrinsic_load_local_invocation_id: {
       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
-      bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
+      if (ctx->options->chip_class >= GFX11) {
+         Temp local_ids[3];
+
+         /* Thread IDs are packed in VGPR0, 10 bits per component. */
+         for (uint32_t i = 0; i < 3; i++) {
+            local_ids[i] = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
+                                    get_arg(ctx, ctx->args->ac.local_invocation_ids),
+                                    Operand::c32(i * 10u), Operand::c32(10u));
+         }
+
+         bld.pseudo(aco_opcode::p_create_vector, Definition(dst), local_ids[0], local_ids[1],
+                    local_ids[2]);
+      } else {
+         bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
+      }
       emit_split_vector(ctx, dst, 3);
       break;
    }
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index 2a91ab71f25..d07898217c3 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -597,7 +597,10 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
       }
 
-      ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT, &args->ac.local_invocation_ids);
+      if (chip_class >= GFX11)
+         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.local_invocation_ids);
+      else
+         ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT, &args->ac.local_invocation_ids);
       break;
    case MESA_SHADER_VERTEX:
       /* NGG is handled by the GS case */