Mesa (staging/22.0): tu: Do not flush ccu in clear/blits during renderpass

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Module: Mesa
Branch: staging/22.0
Commit: 5c4f1b25f1fb6a672edeba03fddd5db4396410f8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c4f1b25f1fb6a672edeba03fddd5db4396410f8

Author: Danylo Piliaiev <dpiliaiev at igalia.com>
Date:   Thu May  5 20:29:05 2022 +0300

tu: Do not flush ccu in clear/blits during renderpass

For clear/blits ccu flush not only worse for perf, but also messes up
flush_bits when executed in a conditional set of commands.

We already don't flush for 3d blits.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6419

Fixes: 487aa807bd1b70602fcb6fbdabd101d4cff7c07b
("tu: Rewrite flushing to use barriers")

Signed-off-by: Danylo Piliaiev <dpiliaiev at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16352>
(cherry picked from commit 187d3df52c77b92bb8002f90818b0a9fce8a7e1a)

---

 .pick_status.json                    | 2 +-
 src/freedreno/vulkan/tu_clear_blit.c | 4 +++-
 src/freedreno/vulkan/tu_cmd_buffer.c | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 91f03ed2711..8b2a3a61803 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1524,7 +1524,7 @@
         "description": "tu: Do not flush ccu in clear/blits during renderpass",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "because_sha": "487aa807bd1b70602fcb6fbdabd101d4cff7c07b"
     },
     {
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index 7aa9540a4af..18b1a3da47b 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -303,7 +303,9 @@ r2d_setup(struct tu_cmd_buffer *cmd,
 {
    assert(samples == VK_SAMPLE_COUNT_1_BIT);
 
-   tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
+   if (!cmd->state.pass) {
+      tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
+   }
 
    r2d_setup_common(cmd, cs, format, aspect_mask, blit_param, clear, ubwc, false);
 }
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index cea2464b345..bb443b1d935 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -159,6 +159,8 @@ tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
    enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
 
    assert(ccu_state != TU_CMD_CCU_UNKNOWN);
+   /* It's unsafe to flush inside condition because we clear flush_bits */
+   assert(!cs->cond_flags);
 
    /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
     * the CCU may also contain data that we haven't flushed out yet, so we