Mesa (main): ir3, freedreno, tu: Make ir3_shader_variant store stream_output
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Fri May 13 17:52:17 UTC 2022
Module: Mesa
Branch: main
Commit: 3e30608cebca6de4bd278bc0cdc778ecb3801339
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e30608cebca6de4bd278bc0cdc778ecb3801339
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Feb 16 11:42:58 2022 +0100
ir3, freedreno, tu: Make ir3_shader_variant store stream_output
This reduces the number of uses of ir3_shader which will be gone when we
deserialize the variant directly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16147>
---
src/freedreno/ir3/ir3_compiler_nir.c | 4 ++--
src/freedreno/ir3/ir3_nir.c | 4 ++--
src/freedreno/ir3/ir3_shader.c | 3 ++-
src/freedreno/ir3/ir3_shader.h | 3 +++
src/freedreno/vulkan/tu_pipeline.c | 4 ++--
src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 2 +-
src/gallium/drivers/freedreno/a5xx/fd5_emit.h | 2 +-
src/gallium/drivers/freedreno/a5xx/fd5_program.c | 4 ++--
src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 2 +-
src/gallium/drivers/freedreno/a6xx/fd6_program.c | 10 +++++-----
src/gallium/drivers/freedreno/a6xx/fd6_program.h | 2 +-
src/gallium/drivers/freedreno/ir3/ir3_const.h | 2 +-
src/gallium/drivers/freedreno/ir3/ir3_gallium.c | 4 ++--
13 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 933ef90cba7..d8d0bcd85b7 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3756,7 +3756,7 @@ static void
emit_stream_out(struct ir3_context *ctx)
{
struct ir3 *ir = ctx->ir;
- struct ir3_stream_output_info *strmout = &ctx->so->shader->stream_output;
+ struct ir3_stream_output_info *strmout = &ctx->so->stream_output;
struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
@@ -3894,7 +3894,7 @@ emit_function(struct ir3_context *ctx, nir_function_impl *impl)
* out instructions.
*/
if ((ctx->compiler->gen < 5) &&
- (ctx->so->shader->stream_output.num_outputs > 0) &&
+ (ctx->so->stream_output.num_outputs > 0) &&
!ctx->so->binning_pass) {
debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
emit_stream_out(ctx);
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 61be4a37037..ebda680e2d3 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -840,7 +840,7 @@ ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
ir3_nir_scan_driver_consts(compiler, nir, const_state);
- if ((compiler->gen < 5) && (v->shader->stream_output.num_outputs > 0)) {
+ if ((compiler->gen < 5) && (v->stream_output.num_outputs > 0)) {
const_state->num_driver_params =
MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
}
@@ -892,7 +892,7 @@ ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
}
if ((v->type == MESA_SHADER_VERTEX) && (compiler->gen < 5) &&
- v->shader->stream_output.num_outputs > 0) {
+ v->stream_output.num_outputs > 0) {
const_state->offsets.tfbo = constoff;
constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
}
diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c
index 002ad27c1f0..bb8d67d8a0c 100644
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -334,6 +334,7 @@ alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
v->key = *key;
v->type = shader->type;
v->mergedregs = shader->compiler->gen >= 6;
+ v->stream_output = shader->stream_output;
if (!v->binning_pass)
v->const_state = rzalloc_size(v, sizeof(*v->const_state));
@@ -855,7 +856,7 @@ void
ir3_link_stream_out(struct ir3_shader_linkage *l,
const struct ir3_shader_variant *v)
{
- const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
+ const struct ir3_stream_output_info *strmout = &v->stream_output;
/*
* First, any stream-out varyings not already in linkage map (ie. also
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index f543d8316d5..a28f48902ad 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -731,6 +731,9 @@ struct ir3_shader_variant {
/* Important for compute shader to determine max reg footprint */
bool has_barrier;
+ /* For when we don't have a shader, variant's copy of streamout state */
+ struct ir3_stream_output_info stream_output;
+
struct ir3_disasm_info disasm_info;
};
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index abe232e56f7..81655b37393 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -779,7 +779,7 @@ tu6_setup_streamout(struct tu_cs *cs,
const struct ir3_shader_variant *v,
struct ir3_shader_linkage *l)
{
- const struct ir3_stream_output_info *info = &v->shader->stream_output;
+ const struct ir3_stream_output_info *info = &v->stream_output;
/* Note: 64 here comes from the HW layout of the program RAM. The program
* for stream N is at DWORD 64 * N.
*/
@@ -1016,7 +1016,7 @@ tu6_emit_vpc(struct tu_cs *cs,
if (fs)
ir3_link_shaders(&linkage, last_shader, fs, true);
- if (last_shader->shader->stream_output.num_outputs)
+ if (last_shader->stream_output.num_outputs)
ir3_link_stream_out(&linkage, last_shader);
/* We do this after linking shaders in order to know whether PrimID
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 5caaf9d5d5f..46ae6f18c58 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -723,7 +723,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
if (!emit->binning_pass)
ir3_emit_fs_consts(fp, ring, ctx);
- struct ir3_stream_output_info *info = &vp->shader->stream_output;
+ const struct ir3_stream_output_info *info = &vp->stream_output;
if (info->num_outputs) {
struct fd_streamout_stateobj *so = &ctx->streamout;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
index b91d8d0c929..e4f33d012b2 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
@@ -85,7 +85,7 @@ fd5_emit_get_vp(struct fd5_emit *emit)
* is what has all the outputs that might be involved in TFB.
*/
if (emit->binning_pass &&
- !emit->prog->vs->shader->stream_output.num_outputs)
+ !emit->prog->vs->stream_output.num_outputs)
emit->vs = emit->prog->bs;
else
emit->vs = emit->prog->vs;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index c55e3403bea..2b7fb722ac2 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -88,7 +88,7 @@ static void
emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
struct ir3_shader_linkage *l)
{
- const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
+ const struct ir3_stream_output_info *strmout = &v->stream_output;
unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
unsigned prog[align(l->max_loc, 2) / 2];
@@ -249,7 +249,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
setup_stages(emit, s);
- bool do_streamout = (s[VS].v->shader->stream_output.num_outputs > 0);
+ bool do_streamout = (s[VS].v->stream_output.num_outputs > 0);
uint8_t clip_mask = s[VS].v->clip_mask,
cull_mask = s[VS].v->cull_mask;
uint8_t clip_cull_mask = clip_mask | cull_mask;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index fc2d8bb9f1b..ba894290e08 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -856,7 +856,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
{
struct fd_context *ctx = emit->ctx;
const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
- struct ir3_stream_output_info *info = prog->stream_output;
+ const struct ir3_stream_output_info *info = prog->stream_output;
struct fd_streamout_stateobj *so = &ctx->streamout;
emit->streamout_mask = 0;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 33264d77799..68cf39e1b59 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -189,7 +189,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
const struct ir3_shader_variant *v,
struct ir3_shader_linkage *l)
{
- const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
+ const struct ir3_stream_output_info *strmout = &v->stream_output;
/* Note: 64 here comes from the HW layout of the program RAM. The program
* for stream N is at DWORD 64 * N.
@@ -580,7 +580,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
struct ir3_shader_linkage l = {0};
const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
- bool do_streamout = (last_shader->shader->stream_output.num_outputs > 0);
+ bool do_streamout = (last_shader->stream_output.num_outputs > 0);
uint8_t clip_mask = last_shader->clip_mask,
cull_mask = last_shader->cull_mask;
uint8_t clip_cull_mask = clip_mask | cull_mask;
@@ -1248,7 +1248,7 @@ fd6_program_create(void *data, struct ir3_shader_variant *bs,
* binning pass VS will have outputs on other than position/psize
* stripped out:
*/
- state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
+ state->bs = vs->stream_output.num_outputs ? vs : bs;
state->vs = vs;
state->hs = hs;
state->ds = ds;
@@ -1285,8 +1285,8 @@ fd6_program_create(void *data, struct ir3_shader_variant *bs,
setup_stateobj(state->stateobj, ctx, state, key, false);
state->interp_stateobj = create_interp_stateobj(ctx, state);
- struct ir3_stream_output_info *stream_output =
- &fd6_last_shader(state)->shader->stream_output;
+ const struct ir3_stream_output_info *stream_output =
+ &fd6_last_shader(state)->stream_output;
if (stream_output->num_outputs > 0)
state->stream_output = stream_output;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.h b/src/gallium/drivers/freedreno/a6xx/fd6_program.h
index 0bfd9ea3ebe..0f17f602651 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.h
@@ -50,7 +50,7 @@ struct fd6_program_state {
struct fd_ringbuffer *streamout_stateobj;
struct fd_ringbuffer *stateobj;
- struct ir3_stream_output_info *stream_output;
+ const struct ir3_stream_output_info *stream_output;
/**
* Output components from frag shader. It is possible to have
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_const.h b/src/gallium/drivers/freedreno/ir3/ir3_const.h
index 716fc32a7a0..2b2a870135a 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_const.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_const.h
@@ -367,7 +367,7 @@ emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
uint32_t offset = const_state->offsets.tfbo;
if (v->constlen > offset) {
struct fd_streamout_stateobj *so = &ctx->streamout;
- struct ir3_stream_output_info *info = &v->shader->stream_output;
+ const struct ir3_stream_output_info *info = &v->stream_output;
uint32_t params = 4;
uint32_t offsets[params];
struct fd_bo *bos[params];
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
index fbde261b14e..8625625c835 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
@@ -585,10 +585,10 @@ ir3_update_max_tf_vtx(struct fd_context *ctx,
const struct ir3_shader_variant *v)
{
struct fd_streamout_stateobj *so = &ctx->streamout;
- struct ir3_stream_output_info *info = &v->shader->stream_output;
+ const struct ir3_stream_output_info *info = &v->stream_output;
uint32_t maxvtxcnt = 0x7fffffff;
- if (v->shader->stream_output.num_outputs == 0)
+ if (v->stream_output.num_outputs == 0)
maxvtxcnt = 0;
if (so->num_targets == 0)
maxvtxcnt = 0;
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