Mesa (main): radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU

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Module: Mesa
Branch: main
Commit: a8d2ef8bd6e34eef4dbab1a078ea27d35538d554
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8d2ef8bd6e34eef4dbab1a078ea27d35538d554

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat May 14 02:19:56 2022 -0400

radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU

GS_PIPELINE_STATS_EMU is always false, so the branches were never entered.

Reviewed-by: Mihai Preda <mhpreda at gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>

---

 src/gallium/drivers/radeonsi/gfx10_shader_ngg.c | 84 +++++++++++++------------
 1 file changed, 44 insertions(+), 40 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
index 05034684ee0..0185a8194ac 100644
--- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
+++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
@@ -1853,27 +1853,29 @@ void gfx10_ngg_gs_emit_begin(struct si_shader_context *ctx)
    }
    ac_build_endif(&ctx->ac, 5090);
 
-   tmp = si_is_gs_thread(ctx);
-   ac_build_ifcc(&ctx->ac, tmp, 15090);
-      {
-         tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
-         tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
-         ac_build_ifcc(&ctx->ac, tmp, 5109); /* if (GS_PIPELINE_STATS_EMU) */
-         LLVMValueRef args[] = {
-            ctx->ac.i32_1,
-            ngg_get_emulated_counters_buf(ctx),
-            LLVMConstInt(ctx->ac.i32,
-                         (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_INVOCATIONS) +
-                             SI_QUERY_STATS_END_OFFSET_DW) * 4,
-                         false),
-            ctx->ac.i32_0,                            /* soffset */
-            ctx->ac.i32_0,                            /* cachepolicy */
-         };
-
-         ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
-         ac_build_endif(&ctx->ac, 5109);
-      }
-   ac_build_endif(&ctx->ac, 15090);
+   if (ctx->screen->info.gfx_level < GFX11) {
+      tmp = si_is_gs_thread(ctx);
+      ac_build_ifcc(&ctx->ac, tmp, 15090);
+         {
+            tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
+            tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
+            ac_build_ifcc(&ctx->ac, tmp, 5109); /* if (GS_PIPELINE_STATS_EMU) */
+            LLVMValueRef args[] = {
+               ctx->ac.i32_1,
+               ngg_get_emulated_counters_buf(ctx),
+               LLVMConstInt(ctx->ac.i32,
+                            (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_INVOCATIONS) +
+                                SI_QUERY_STATS_END_OFFSET_DW) * 4,
+                            false),
+               ctx->ac.i32_0,                            /* soffset */
+               ctx->ac.i32_0,                            /* cachepolicy */
+            };
+
+            ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
+            ac_build_endif(&ctx->ac, 5109);
+         }
+      ac_build_endif(&ctx->ac, 15090);
+   }
 
    ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM);
    ac_build_s_barrier(&ctx->ac, ctx->stage);
@@ -2183,26 +2185,28 @@ void gfx10_ngg_gs_build_end(struct si_shader_context *ctx)
 
       ac_build_export_prim(&ctx->ac, &prim);
 
-      tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
-      tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
-      ac_build_ifcc(&ctx->ac, tmp, 5229); /* if (GS_PIPELINE_STATS_EMU) */
-      ac_build_ifcc(&ctx->ac, LLVMBuildNot(builder, prim.isnull, ""), 5237);
-      {
-         LLVMValueRef args[] = {
-            ctx->ac.i32_1,
-            ngg_get_emulated_counters_buf(ctx),
-            LLVMConstInt(ctx->ac.i32,
-                         (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_PRIMITIVES) +
-                             SI_QUERY_STATS_END_OFFSET_DW) * 4,
-                         false),
-            ctx->ac.i32_0,                            /* soffset */
-            ctx->ac.i32_0,                            /* cachepolicy */
-         };
-
-         ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
+      if (ctx->screen->info.gfx_level < GFX11) {
+         tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
+         tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
+         ac_build_ifcc(&ctx->ac, tmp, 5229); /* if (GS_PIPELINE_STATS_EMU) */
+         ac_build_ifcc(&ctx->ac, LLVMBuildNot(builder, prim.isnull, ""), 5237);
+         {
+            LLVMValueRef args[] = {
+               ctx->ac.i32_1,
+               ngg_get_emulated_counters_buf(ctx),
+               LLVMConstInt(ctx->ac.i32,
+                            (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_PRIMITIVES) +
+                                SI_QUERY_STATS_END_OFFSET_DW) * 4,
+                            false),
+               ctx->ac.i32_0,                            /* soffset */
+               ctx->ac.i32_0,                            /* cachepolicy */
+            };
+
+            ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
+         }
+         ac_build_endif(&ctx->ac, 5237);
+         ac_build_endif(&ctx->ac, 5229);
       }
-      ac_build_endif(&ctx->ac, 5237);
-      ac_build_endif(&ctx->ac, 5229);
    }
    ac_build_endif(&ctx->ac, 5140);