Mesa (main): radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs

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Module: Mesa
Branch: main
Commit: a529e4f7ada2c3c2de632b2f9553538b7a27c9ec
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a529e4f7ada2c3c2de632b2f9553538b7a27c9ec

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat May 14 02:33:30 2022 -0400

radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs

Reviewed-by: Mihai Preda <mhpreda at gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>

---

 src/gallium/drivers/radeonsi/si_gfx_cs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 5fb7eef195e..7cc718fd452 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -304,7 +304,11 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
 
    /* Set all cleared context registers to saved. */
    ctx->tracked_regs.reg_saved = BITFIELD64_MASK(SI_TRACKED_GE_PC_ALLOC);
-   ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
+
+   if (ctx->gfx_level >= GFX11)
+      ctx->last_gs_out_prim = -1; /* uconfig register, unknown value */
+   else
+      ctx->last_gs_out_prim = 0; /* context register cleared by CLEAR_STATE */
 }
 
 void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_vbo_func wrapper,