Mesa (main): 34 new commits

Thu May 19 16:24:15 UTC 2022

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6ece34d0c3329c6518633dacec338a19e8f5e38
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 9 16:03:27 2022 -0400

    pan/va: Use ^ instead of ` to indicate last-use
    
    This syncs the ISA syntax with other Valhall ISA users. It's also somewhat
    easier to read.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fb8ca1851b2670fa019ea01dc8c549a812e3e87
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 18 11:57:55 2022 -0400

    pan/va: Remove DISCARD.f32 destination
    
    It doesn't actually write anything. This is a pointless divergence from Bifrost.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=444469d64e0f42bcf2bba0b7ba19cce667a19542
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 16 09:43:34 2022 -0400

    pan/va: Handle 2-src blend in lower_split_src
    
    Fixes assertion fail in shaders/dolphin/smg.1.shader_test
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0576cad958b459701a5dde73ac2f27afb91fe391
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Thu May 12 20:21:42 2022 -0400

    pan/bi: Validate vector widths
    
    Now that our IR is much more strongly typed, and RA code quality depends on
    correct typing, add a validation pass to make sure we didn't screw it up. This
    pass found a massive number of bugs in early versions of this series.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c1bb23a86b0531c096c40017ced194880e6cf8c
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 15:47:39 2022 -0400

    pan/bi: Validate preload constraints are satisfied
    
    We tightened the rules around preloading substantially and take advantage of the
    rules in RA. The safe helpers it introduced should ensure the rules are
    followed, but just in case, add a validation pass to check our work. This pass
    found (multiple) bugs in early versions of this series.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3636cddde1658ae56cad498940d3264c4c364cd3
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Fri May 13 11:54:19 2022 -0400

    pan/bi: See through splits for var_tex fusion
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f25f78a9feff41380aa7cf031c3bfd5be67433b
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Thu May 12 13:10:57 2022 -0400

    pan/bi: Optimize split of collect
    
    Required to get decent codegen from UBO pushing.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a8bde21904df4b31e25af98b3202448655973bf
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Thu May 12 12:37:00 2022 -0400

    pan/bi: Don't propagate discard
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d81b872465722b5aa096a46c014e2700a9d04217
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 17:12:13 2022 -0400

    pan/bi: Remove liveness metadata tracking
    
    We don't use it for anything, and with no pass infrastructure it's just an
    accident waiting to happen.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3df5446cbd460aee6c02c570ecbc285102abc9f0
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 15:39:56 2022 -0400

    pan/bi: Simplify register precolouring in the IR
    
    In the current IR, any register may be preloaded by reading it anywhere, and any
    register may be precoloured by writing it anywhere. This is convenient for
    instruction selection, but requires the register allocator to do considerable
    gymnastics to ensure it doesn't clobber precoloured registers. It also breaks
    the purity of our SSA representation, which complicates optimization passes
    (e.g. copyprop).
    
    Let's trade some instruction selection complexity for simplifying register
    allocation by constraining how register precolouring works. Under the new model:
    
    * Registers may only be preloaded at the start of the program.
    * Precoloured destinations are handled explicitly by RA.
    
    Internally, a stronger invariant is placed for preloading: registers may only be
    preloaded by MOV.i32 instructions at the beginning of the block, and these moves
    must be unique. These invariants ensure RA can trivially coalesce the moves.
    
    A bi_preload helper is added as a safe version of bi_register respecting these
    invariants, allowing a smooth transition for instruction selection.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dab5b62ecf966e3dd65af6ea0e27bec3aa89881d
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:21:38 2022 -0400

    pan/bi: Remove bi_word and bi_word_node
    
    They are no longer used, as offsets are no longer used for normal values (only for
    FAU). Keep it like that.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0184cf218fe5c96c7294f75efb6011394eb30bf
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:26:42 2022 -0400

    pan/bi: Scalarize copyprop
    
    Reduces memory footprint.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6349278f97f026d3b784092d56de058eb47efd5
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:24:31 2022 -0400

    pan/bi: Scalarize modifier propagation
    
    Reduces memory footprint.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e332e2edc174159b1eed71de6aef87848ba2439b
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:24:22 2022 -0400

    pan/bi: Scalarize bi_opt_cse
    
    Reduces memory footprint.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=187dd382cbb5590f053e1955aa4e344b8aed83de
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:22:10 2022 -0400

    pan/bi: Scalarize bi_lower_swizzle
    
    Reduces memory footprint.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b1c642cee9651edb9113f669d9de9b058921609
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:18:36 2022 -0400

    pan/va: Don't use bi_word in FAU unit test
    
    It will be removed shortly, as the FAU construction helper should be used
    instead.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=67569b3c236852789264049fb91b6d04db4ea271
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 12:15:54 2022 -0400

    pan/va: Use split for 64-bit lowering
    
    Written in this way, this pass looks pretty silly...
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5febeae58e0a133f048cb0e2d1ef45549851bea4
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Tue May 10 12:22:48 2022 -0400

    pan/bi: Emit collect and split
    
    ..Rather than using offsets during instruction selection.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4731e9e55a26dc7105b8b6316b3dc14f5bc8aa28
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Tue May 10 12:23:28 2022 -0400

    pan/bi: Simplfy BLEND emit
    
    We don't need to collect anything, now that Valhall handles this case correctly.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bfaa119f45619659b24cb9b6db2dfdc6d4e21a7
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Tue May 10 11:54:03 2022 -0400

    pan/bi: Lift split/collect cache from AGX
    
    Design based on ACO (and fruitful discussions with Daniel).
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fdb01b96f1534ca0663f2ebe3b2b8c3246bb0f2
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Tue May 10 10:03:16 2022 -0400

    pan/bi: Create COLLECT during isel
    
    This transitions us away from the fake SSA we currently use for vectors.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c0977d2304b299c4c7dc2c93f13ce51c097db78
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Tue May 10 12:21:58 2022 -0400

    pan/bi: Expand MAX_DESTS to 4
    
    For splits.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9924e6f291496e1c53a1691bc371c99b0f49964b
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 18 12:44:38 2022 -0400

    pan/bi: Fix mov and pack_32_2x16
    
    Move can take in a vector and write a scalar, depending on the swizzle. We need
    to handle this case. Split out mov and pack_32_2x16 so we can specify correct
    behaviour for both. Also drop unused 1-bit boolean stuff which obscured the fix.
    
    Fixes: 76cea8e27b3 ("panfrost: Fix pack_32_2x16 implementation")
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc17288697f87830f533c2a55ba3503e7423d53a
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 16 14:17:51 2022 -0400

    pan/bi: Lower split/collect before RA
    
    For transitioning to the new scalarized IR.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c7f12627748aa56fc051154e77e9ecfb3ed2d70
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 11 15:39:38 2022 -0400

    pan/bi: Add bi_before_block cursor
    
    Useful for preloading.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=298d20f805cbe44f1bad6fe4e7ff70eb31a8c335
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 9 17:00:11 2022 -0400

    pan/bi: Add collect and split instructions
    
    These move-like instructions will be generated during instruction selection and
    lowered before/after register allocation.
    
    These need special printer support until we get dynamic sources/destinations.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=afd88d138040788c1be244d7821b2357a6502754
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 9 17:28:38 2022 -0400

    pan/bi: Add source/destination counts
    
    In preparation for dynamic allocation, as needed for phi nodes and parallel
    copies. For now, it just serves to simplify the semantics of splits and
    collects.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0523b6b89ba487a00102be8e16c7c622623419c9
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 18 10:52:29 2022 -0400

    pan/bi: Use value-based interference with LCRA
    
    "Revisiting Out-of-SSA Translation for Correctness, Code Quality, and
    Efficiency" discusses "value-based interference": two variables interfere if and
    only if there exists a point in the program where they are both live *with
    different values*. In particular, the source and destination of a move do not
    interfere a priori, because they have the same value at that point in the
    program. (If a later instruction overwrites one, the required interference will
    be added there).
    
    We can use this idea to avoid some extra interferences, avoiding a regression in
    moves from split/collect.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=896dc63623bf19a6260d2ec0dd51cd0ab271bb17
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 18 09:42:41 2022 -0400

    pan/bi: Lower phis to scalar
    
    If we don't lower phis to scalar, when we go out of SSA, we can get vector
    nir_registers. In particular, we can get code like:
    
       r0 = vec2 r0.y, r0.x
    
    This code looks like a move, but is in fact a swap. The trivial lowering of vec2
    would not work -- the following fails to swap correctly:
    
       r0.x = r0.y
       r0.y = r0.x
    
    Currently, we generate temporaries to handle these cases. It's easy to move the
    complexity to NIR, though, and we'll want to scalarize phis for SSA-based RA
    anyway.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8882ee11503689c453912d1462208e95339c262
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed May 18 11:02:53 2022 -0400

    pan/bi: +JUMP can't read same-cycle temp
    
    Minor ISA detail missed in the Bifrost scheduler. I hit this in an early version
    of this series (where a move feeding into a blend shader return was not
    coalesced). Let's get it fixed in the scheduler.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c387096eca0bddc83946c56505d51a54752806ce
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 9 15:56:25 2022 -0400

    pan/va: Use 64-bit lowering for texturing
    
    Texture instructions on Valhall take 64-bit sources. Now that we have
    infrastructure to handle this properly, we don't need to use a non-SSA node to
    hack around the optimization.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=89a3746bc112d3ae78f55455a74e55cf5ccee3e3
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 9 10:17:00 2022 -0400

    pan/va: Lower split 64-bit sources
    
    This ensures Valhall 64-bit constraints are respected in a simple way. It's not
    the most efficient, though. Optimization is deferred until full Valhall support
    is upstreamed and the RA is overhauled.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=65839d8c3ce8e58ab259e13baa95425b55620aa6
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon May 9 10:21:41 2022 -0400

    pan/va: Mark more source sizes
    
    This source size information will be consumed by the 64-bit lowering pass, so
    ensure it's accurate. That means marking 32-bit and 64-bit sources explicitly on
    message passing where it wouldn't match up with the type size suffix of the
    instruction.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=04a1df8c65de410ea3dd0283f3d8e045fb706d92
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed Mar 23 12:05:10 2022 -0400

    pan/bi: Update bi_count_write_registers for Valhall
    
    We add some new instructions on Valhall with special register requirements
    (texturing, atomics). Handle these appropriately so we can do RA on Valhall.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>