Mesa (main): freedreno/ir3: Add support for 16-bit nir_texop_lod.

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Module: Mesa
Branch: main
Commit: 1cf0736f1c44ae3cd53163a4a21ed290a2c0836c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cf0736f1c44ae3cd53163a4a21ed290a2c0836c

Author: Emma Anholt <emma at anholt.net>
Date:   Wed May 11 19:55:45 2022 -0700

freedreno/ir3: Add support for 16-bit nir_texop_lod.

Same basic path, just do the rescaling in half float.

Reviewed-by: Matt Turner <mattst88 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465>

---

 src/freedreno/ir3/ir3_compiler_nir.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 5a02af2e253..23dc383828c 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3280,12 +3280,15 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
 
    /* GETLOD returns results in 4.8 fixed point */
    if (opc == OPC_GETLOD) {
-      struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
+      bool half = nir_dest_bit_size(tex->dest) == 16;
+      struct ir3_instruction *factor =
+         half ? create_immed_typed(b, _mesa_float_to_half(1.0 / 256), TYPE_F16)
+              : create_immed(b, fui(1.0 / 256));
 
-      compile_assert(ctx, tex->dest_type == nir_type_float32);
       for (i = 0; i < 2; i++) {
-         dst[i] =
-            ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0, factor, 0);
+         dst[i] = ir3_MUL_F(
+            b, ir3_COV(b, dst[i], TYPE_S32, half ? TYPE_F16 : TYPE_F32), 0,
+            factor, 0);
       }
    }