Mesa (main): radv: update VRS rates on GFX11

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Module: Mesa
Branch: main
Commit: f7b1ad7c06d24a4521a6d64e1e9f10888f4d1fd8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7b1ad7c06d24a4521a6d64e1e9f10888f4d1fd8

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue May 10 15:02:57 2022 +0200

radv: update VRS rates on GFX11

GFX11 uses enum instead of 2-bit integer numbers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
iReviewed-by: Timur Kristóf <timur.kristof at gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>

---

 src/amd/vulkan/radv_cmd_buffer.c |  7 +++---
 src/amd/vulkan/radv_shader.c     | 48 +++++++++++++++++++++++-----------------
 2 files changed, 32 insertions(+), 23 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7596fe60a98..e87ab42b2b0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3686,6 +3686,7 @@ static void
 radv_flush_force_vrs_state(struct radv_cmd_buffer *cmd_buffer)
 {
    struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
+   enum amd_gfx_level gfx_level = pipeline->base.device->physical_device->rad_info.gfx_level;
    const unsigned stage = pipeline->last_vgt_api_stage;
    struct radv_userdata_info *loc;
    uint32_t vrs_rates = 0;
@@ -3704,13 +3705,13 @@ radv_flush_force_vrs_state(struct radv_cmd_buffer *cmd_buffer)
 
    switch (cmd_buffer->device->force_vrs) {
    case RADV_FORCE_VRS_2x2:
-      vrs_rates = (1u << 2) | (1u << 4);
+      vrs_rates = gfx_level >= GFX11 ? V_0283D0_VRS_SHADING_RATE_2X2 : (1u << 2) | (1u << 4);
       break;
    case RADV_FORCE_VRS_2x1:
-      vrs_rates = (1u << 2) | (0u << 4);
+      vrs_rates = gfx_level >= GFX11 ? V_0283D0_VRS_SHADING_RATE_2X1 : (1u << 2) | (0u << 4);
       break;
    case RADV_FORCE_VRS_1x2:
-      vrs_rates = (0u << 2) | (1u << 4);
+      vrs_rates = gfx_level >= GFX11 ? V_0283D0_VRS_SHADING_RATE_1X2 : (0u << 2) | (1u << 4);
       break;
    default:
       break;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index ec6fb429c15..d4867958e1f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -342,7 +342,7 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key)
 }
 
 static bool
-radv_lower_primitive_shading_rate(nir_shader *nir)
+radv_lower_primitive_shading_rate(nir_shader *nir, enum amd_gfx_level gfx_level)
 {
    nir_function_impl *impl = nir_shader_get_entrypoint(nir);
    bool progress = false;
@@ -381,27 +381,34 @@ radv_lower_primitive_shading_rate(nir_shader *nir)
 
          nir_ssa_def *out = NULL;
 
+         /* MS:
+          * Primitive shading rate is a per-primitive output, it is
+          * part of the second channel of the primitive export.
+          * Bits [28:31] = VRS rate
+          * This will be added to the other bits of that channel in the backend.
+          *
+          * VS, TES, GS:
+          * Primitive shading rate is a per-vertex output pos export.
+          * Bits [2:5] = VRS rate
+          * HW shading rate = (xRate << 2) | (yRate << 4)
+          *
+          * GFX11: 4-bit VRS_SHADING_RATE enum
+          * GFX10: X = low 2 bits, Y = high 2 bits
+          */
+         unsigned x_rate_shift = 2;
+         unsigned y_rate_shift = 4;
+
+         if (gfx_level >= GFX11) {
+            x_rate_shift = 4;
+            y_rate_shift = 2;
+         }
          if (nir->info.stage == MESA_SHADER_MESH) {
-            /* MS:
-             * Primitive shading rate is a per-primitive output, it is
-             * part of the second channel of the primitive export.
-             *
-             * Bits [28:29] = VRS rate X
-             * Bits [30:31] = VRS rate Y
-             * This will be added to the other bits of that channel in the backend.
-             */
-            out = nir_ior(&b, nir_ishl_imm(&b, x_rate, 28), nir_ishl_imm(&b, y_rate, 30));
-         } else {
-            /* VS, TES, GS:
-             * Primitive shading rate is a per-vertex output pos export.
-             *
-             * Bits [2:3] = VRS rate X
-             * Bits [4:5] = VRS rate Y
-             * HW shading rate = (xRate << 2) | (yRate << 4)
-             */
-            out = nir_ior(&b, nir_ishl_imm(&b, x_rate, 2), nir_ishl_imm(&b, y_rate, 4));
+            x_rate_shift += 26;
+            y_rate_shift += 26;
          }
 
+         out = nir_ior(&b, nir_ishl_imm(&b, x_rate, x_rate_shift), nir_ishl_imm(&b, y_rate, y_rate_shift));
+
          nir_instr_rewrite_src(&intr->instr, &intr->src[1], nir_src_for_ssa(out));
 
          progress = true;
@@ -937,7 +944,8 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_
         nir->info.stage == MESA_SHADER_MESH) &&
        nir->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE)) {
       /* Lower primitive shading rate to match HW requirements. */
-      NIR_PASS(_, nir, radv_lower_primitive_shading_rate);
+      NIR_PASS(_, nir, radv_lower_primitive_shading_rate,
+               device->physical_device->rad_info.gfx_level);
    }
 
    /* Indirect lowering must be called after the radv_optimize_nir() loop