Mesa (main): pan/bi: Don't allow spilling coverage mask writes
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Mon May 30 14:16:25 UTC 2022
Module: Mesa
Branch: main
Commit: 42a4a123a6f5436537e2689472db8c68da18c5d9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=42a4a123a6f5436537e2689472db8c68da18c5d9
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri May 27 11:36:01 2022 -0400
pan/bi: Don't allow spilling coverage mask writes
The register precolouring logic assumes that coverage masks are always in R60,
so spilling them causes incorrect results. We could do better. Fixes on Valhall:
dEQP-GLES3.functional.ubo.random.all_per_block_buffers.28
Fixes: 3df5446cbd4 ("pan/bi: Simplify register precolouring in the IR")
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16748>
---
src/panfrost/bifrost/bi_ra.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c
index 253ac85c789..87f5ab1b35f 100644
--- a/src/panfrost/bifrost/bi_ra.c
+++ b/src/panfrost/bifrost/bi_ra.c
@@ -497,8 +497,21 @@ bi_choose_spill_node(bi_context *ctx, struct lcra_state *l)
bi_foreach_dest(ins, d) {
unsigned node = bi_get_node(ins->dest[d]);
- if (node < l->node_count && ins->no_spill)
+ if (node >= l->node_count)
+ continue;
+
+ /* Don't allow spilling coverage mask writes because the
+ * register preload logic assumes it will stay in R60.
+ * This could be optimized.
+ */
+ if (ins->no_spill ||
+ ins->op == BI_OPCODE_ATEST ||
+ ins->op == BI_OPCODE_ZS_EMIT ||
+ (ins->op == BI_OPCODE_MOV_I32 &&
+ ins->src[0].type == BI_INDEX_REGISTER &&
+ ins->src[0].value == 60)) {
BITSET_SET(no_spill, node);
+ }
}
}
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