[Mesa-dev] [RFC] [PATCH 0/3] Make Gallium aware of GL_TEXTURE_RECTANGLE

Alex Deucher alexdeucher at gmail.com
Wed Aug 11 15:39:00 PDT 2010

On Wed, Aug 11, 2010 at 6:34 PM, Marek Olšák <maraeo at gmail.com> wrote:
> On Wed, Aug 11, 2010 at 10:07 PM, Luca Barbieri <luca at luca-barbieri.com>
> wrote:
>> > Because all nvidia hardware seems to have the normalized bit as a
>> > property
>> > of a resource (PIPE_TEXTURE_RECT or a flag would be okay here), and all
>> > ATI
>> > hardware has the normalized bit as part of the texture instruction (it's
>> > a
>> > shader state, so a driver looks for TGSI_TEXTURE_RECT), I believe it
>> > would
>> > really be best for everyone to have this RECT texture target type and
>> > removing normalized_coords from pipe_sampler_state. Luca, you've already
>> > done some work for this change. If you don't have time to finish
>> > PIPE_TEXTURE_RECT, I'll do that.
>> So no hardware at all supports specifying the normalization as part of
>> the sampler state?
>> One has to keep in mind OpenCL though, which has the following API:
>> cl_sampler clCreateSampler (cl_context context,
>>    cl_bool normalized_coords,
>>    cl_addressing_mode addressing_mode,
>>    cl_filter_mode filter_mode, cl_int *errcode_ret)
>> If you put the bit in the resource itself, then it becomes impossible
>> to change the normalization without copying the whole resource, which
>> would seem to be a major problem for implementing OpenCL.
>> A possible solution could be removing the bit from the sampler state
>> and adding the bit to both TEX instructions and sampler views.
>> This would seem to suit nv50, which has it in the hardware sampler
>> view, and r300-r700 which has it in the hardware shader instruction
>> (according to you).
> http://www.x.org/docs/AMD/r600isa.pdf
> Page 301 (335 of the PDF): TEX_DWORD1, the 4 last bit fields.
> It looks like AMD were outvoted in the OpenCL spec.
> Is R800 different? I don't know.

It's the same:
page 2-56.


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