[Mesa-dev] [PATCH 5/5] r600g: set hardware pixel centers according to gl_rasterization_rules

[Alex Deucher]

On Tue, Nov 2, 2010 at 3:40 PM, Keith Whitwell <keithw at vmware.com> wrote:
> These were previously being left in the default (D3D) mode.  This mean
> that triangles were drawn slightly incorrectly, but also because this
> state is relied on by the u_blitter code, all blits were half a pixel
> off.

Looks good.  Evergreen (evergreen_state.c) should be updated similarly.

Alex

> ---
>  src/gallium/drivers/r600/r600_state.c         |    5 +++++
>  src/gallium/drivers/r600/r600d.h              |    4 ++++
>  src/gallium/winsys/r600/drm/r600_hw_context.c |    1 +
>  src/gallium/winsys/r600/drm/r600d.h           |    1 +
>  4 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
> index ccd7421..17e64b1 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -475,6 +475,11 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
>        r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
>        r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
>        r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
> +
> +       r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
> +                               S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
> +                               0xFFFFFFFF, NULL);
> +
>        r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
>        r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
>        r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
> diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
> index a3cb5b8..ae19bfb 100644
> --- a/src/gallium/drivers/r600/r600d.h
> +++ b/src/gallium/drivers/r600/r600d.h
> @@ -2100,6 +2100,10 @@
>  #define   G_028C00_LAST_PIXEL(x)                       (((x) >> 10) & 0x1)
>  #define   C_028C00_LAST_PIXEL                          0xFFFFFBFF
>  #define R_028C04_PA_SC_AA_CONFIG                     0x028C04
> +#define R_028C08_PA_SU_VTX_CNTL                      0x028C08
> +#define   S_028C08_PIX_CENTER_HALF(x)                  (((x) & 0x1) << 0)
> +#define   G_028C08_PIX_CENTER_HALF(x)                  (((x) >> 0) & 0x1)
> +#define   C_028C08_PIX_CENTER_HALF                     0xFFFFFFFE
>  #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
>  #define R_028C48_PA_SC_AA_MASK                       0x028C48
>  #define R_028810_PA_CL_CLIP_CNTL                     0x028810
> diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
> index effb228..c33f81e 100644
> --- a/src/gallium/winsys/r600/drm/r600_hw_context.c
> +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
> @@ -384,6 +384,7 @@ static const struct r600_reg r600_context_reg_list[] = {
>        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
>        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
>        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
> +       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
>        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
>        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
>        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
> diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
> index d91f773..5ca7456 100644
> --- a/src/gallium/winsys/r600/drm/r600d.h
> +++ b/src/gallium/winsys/r600/drm/r600d.h
> @@ -795,6 +795,7 @@
>  #define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
>  #define R_028C00_PA_SC_LINE_CNTL                     0x028C00
>  #define R_028C04_PA_SC_AA_CONFIG                     0x028C04
> +#define R_028C08_PA_SU_VTX_CNTL                      0x028C08
>  #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
>  #define R_028C48_PA_SC_AA_MASK                       0x028C48
>  #define R_028810_PA_CL_CLIP_CNTL                     0x028810
> --
> 1.7.1
>
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