[Mesa-dev] Mesa (shader-work): glsl: introduce ir_binop_all_equal and ir_binop_any_equal, allow vector cmps

[Ian Romanick]

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Luca Barbieri wrote:
>> If you're working on a driver for a scalar chip, you might want to pull
>> brw_fs_channel_expressions and brw_fs_vector_splitting up and get them
>> used -- it should make sensible codegen a lot easier for them.
> 
> Current drivers for scalar hardware take Mesa IR/TGSI input and not GLSL IR.
> 
> Using GLSL IR might be interesting, but how do you plan to support
> assembly programs?
> Will a converter from Mesa IR to GLSL IR be used for that?

Yes.  Post-7.9 we have:

 1. Run directly from GLSL IR for software (where "directly" almost
certainly involves LLVM).

 2. Compile assembly shaders to GLSL IR (possibly via Mesa IR -> GLSL IR
translation).  This will allow support of other NV assembly extensions
for free on more advanced GLSL hardware.  This will give better support
for applications that use Cg.  The GLSL backend for Cg generates some
ugly, ugly code.

 3. Add full support for GLSL 1.30.

 4. Geometry shader support.

 5. Gut prog_execute and fixed-function *software* TNL.

I suspect that #1 and #2 will happen in parallel (I know Ken wants to
work on the converter) so that we can have a single backend in the i965
driver.  #5 depends on #1 and #2 being complete and accepted.  I'm not
sure about the ordering of #3 relative to the others, and #4 depends on
it.  We really want GLSL 1.30 and geometry shaders by the end of the
year.  We'll see if it happens.

> Having two hardware backends, one for GLSL IR, and one for Mesa
> IR/TGSI doesn't seem to be a feasible long-term solution, and dropping
> assembly program support also isn't (e.g. Doom 3 will stop working).
> 
> Also, would converting GLSL IR to LLVM and writing an hardware LLVM
> backend be a better idea?
> That gives an instruction matcher, scalarizer and register allocator
> for free, plus optionally middle-end optimizations.

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