[Mesa-dev] Mesa (shader-work): glsl: introduce ir_binop_all_equal and ir_binop_any_equal, allow vector cmps

Eric Anholt eric at anholt.net
Wed Sep 8 15:35:10 PDT 2010

On Wed, 8 Sep 2010 20:40:24 +0200, Luca Barbieri <luca at luca-barbieri.com> wrote:
> > If you're working on a driver for a scalar chip, you might want to pull
> > brw_fs_channel_expressions and brw_fs_vector_splitting up and get them
> > used -- it should make sensible codegen a lot easier for them.
> Current drivers for scalar hardware take Mesa IR/TGSI input and not GLSL IR.

Yes, but depending on your Mesa IR -> HW codegen, seeing scalar
expressions that have had algebraic optimizations done on them might be
a big win.  Looking at some examples on 965, it's about break-even right
now without fixing up the codegen (but we need to fix up the codegen

> Using GLSL IR might be interesting, but how do you plan to support
> assembly programs?
> Will a converter from Mesa IR to GLSL IR be used for that?

That's part of the plan.

> Having two hardware backends, one for GLSL IR, and one for Mesa
> IR/TGSI doesn't seem to be a feasible long-term solution, and dropping
> assembly program support also isn't (e.g. Doom 3 will stop working).

We've already got 2 Mesa IR backends for the fragment shader in 965,
sadly: the non-flow-control FS that does something like value numbering
to get dead code elimination and copy propagation, and the GLSL one that
still doesn't support function calls and has absolutely ridiculous
register allocation.  So for us, going from 2 to 2 looks OK, and if we
can go from 2 to 1 I can despair about the state of the driver a little

> Also, would converting GLSL IR to LLVM and writing an hardware LLVM
> backend be a better idea?
> That gives an instruction matcher, scalarizer and register allocator
> for free, plus optionally middle-end optimizations.

Structured flow control is the issue.  What's the solution for getting
that back out of LLVM?
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