[Mesa-dev] [PATCH] Implement x86_64 atomics for compilers w/o intrinsics.

[José Fonseca]

I didn't test but looks fine to me. Please commit.

Jose

On Wed, 2010-09-29 at 12:37 -0700, tom fogal wrote:
> ping?
> 
> -tom
> 
> tom fogal <tfogal at sci.utah.edu> writes:
> > A friend of mine had trouble building 7.8.2 on an old gcc3.3 system
> > (no gcc intrinsics).  I put together this patch and he said his build
> > worked.  Our software doesn't thread so it's not really verified
> > otherwise.
> >
> > I was a bit surprised we didn't need int64_t variants for x86_64.
> > Maybe that's needed in general, but just not in swrast / under Mesa
> > w/ our particular option set?
> >
> > Anyway, okay for 7.8 and master?
> >
> > -tom
> > 
> > 
> > ------- =_aaaaaaaaaa0
> > Content-Type: text/x-diff; charset="us-ascii"
> > Content-ID: <7248.1285551879.2 at shigeru.sci.utah.edu>
> > Content-Description: 0001-Implement-x86_64-atomics-for-compilers-w-o-intrinsi
> > c.patch
> > Content-Transfer-Encoding: quoted-printable
> > 
> > =46rom cc32ff741c5d32a66531a586b1f9268b94846c58 Mon Sep 17 00:00:00 2001
> > From: Tom Fogal <tfogal at alumni.unh.edu>
> > Date: Sun, 26 Sep 2010 18:57:59 -0600
> > Subject: [PATCH] Implement x86_64 atomics for compilers w/o intrinsics.
> > 
> > Really old gcc's (3.3, at least) don't have support for the
> > intrinsics we need.  This implements a fallback for that case.
> > ---
> >  src/gallium/auxiliary/util/u_atomic.h |   47 ++++++++++++++++++++++++++++=
> > +++++
> >  1 files changed, 47 insertions(+), 0 deletions(-)
> > 
> > diff --git a/src/gallium/auxiliary/util/u_atomic.h b/src/gallium/auxiliary=
> > /util/u_atomic.h
> > index a156823..8434491 100644
> > --- a/src/gallium/auxiliary/util/u_atomic.h
> > +++ b/src/gallium/auxiliary/util/u_atomic.h
> > @@ -29,6 +29,8 @@
> >  #define PIPE_ATOMIC_ASM_MSVC_X86                =
> > 
> >  #elif (defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86))
> >  #define PIPE_ATOMIC_ASM_GCC_X86
> > +#elif (defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64))
> > +#define PIPE_ATOMIC_ASM_GCC_X86_64
> >  #elif defined(PIPE_CC_GCC) && (PIPE_CC_GCC_VERSION >=3D 401)
> >  #define PIPE_ATOMIC_GCC_INTRINSIC
> >  #else
> > @@ -36,6 +38,51 @@
> >  #endif
> >  =
> > 
> >  =
> > 
> > +#if defined(PIPE_ATOMIC_ASM_GCC_X86_64)
> > +#define PIPE_ATOMIC "GCC x86_64 assembly"
> > +
> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif
> > +
> > +#define p_atomic_set(_v, _i) (*(_v) =3D (_i))
> > +#define p_atomic_read(_v) (*(_v))
> > +
> > +static INLINE boolean
> > +p_atomic_dec_zero(int32_t *v)
> > +{
> > +   unsigned char c;
> > +
> > +   __asm__ __volatile__("lock; decl %0; sete %1":"+m"(*v), "=3Dqm"(c)
> > +			::"memory");
> > +
> > +   return c !=3D 0;
> > +}
> > +
> > +static INLINE void
> > +p_atomic_inc(int32_t *v)
> > +{
> > +   __asm__ __volatile__("lock; incl %0":"+m"(*v));
> > +}
> > +
> > +static INLINE void
> > +p_atomic_dec(int32_t *v)
> > +{
> > +   __asm__ __volatile__("lock; decl %0":"+m"(*v));
> > +}
> > +
> > +static INLINE int32_t
> > +p_atomic_cmpxchg(int32_t *v, int32_t old, int32_t _new)
> > +{
> > +   return __sync_val_compare_and_swap(v, old, _new);
> > +}
> > +
> > +#ifdef __cplusplus
> > +}
> > +#endif
> > +
> > +#endif /* PIPE_ATOMIC_ASM_GCC_X86_64 */
> > +
> >  =
> > 
> >  #if defined(PIPE_ATOMIC_ASM_GCC_X86)
> >  =
> > 
> > -- =
> > 
> > 1.7.0.2
> > 
> > 
> > ------- =_aaaaaaaaaa0
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> > MIME-Version: 1.0
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> > Content-Disposition: inline
> > 
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> > 
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