[Mesa-dev] Mesa (master): i965: clear global offset to zero in m0.2 for VS DP read.

[Zou, Nanhai]

In fact this is not zero at multi vs thread cases on GT1, it will trigger DP read error when multi vs thread is enabled.

I can not find where in spec says this payload M0.2 is reserved as zero,

Thanks
Zou Nan hai

>>-----Original Message-----
>>From: mesa-dev-bounces+nanhai.zou=intel.com at lists.freedesktop.org
>>[mailto:mesa-dev-bounces+nanhai.zou=intel.com at lists.freedesktop.org] On
>>Behalf Of Eric Anholt
>>Sent: 2011年4月9日 1:17
>>To: mesa-dev at lists.freedesktop.org; mesa-commit at lists.freedesktop.org
>>Subject: Re: [Mesa-dev] Mesa (master): i965: clear global offset to zero in
>>m0.2 for VS DP read.
>>
>>On Wed,  6 Apr 2011 22:28:37 -0700 (PDT), znh at kemper.freedesktop.org (Nan hai
>>Zou) wrote:
>>> Module: Mesa
>>> Branch: master
>>> Commit: 66b66295d0bc856c69fdcccc22575580c7ecee16
>>> URL:
>>http://cgit.freedesktop.org/mesa/mesa/commit/?id=66b66295d0bc856c69fdcccc2
>>2575580c7ecee16
>>>
>>> Author: Zou Nan hai <nanhai.zou at intel.com>
>>> Date:   Thu Apr  7 21:07:57 2011 +0800
>>>
>>> i965:   clear global offset to zero in m0.2 for VS DP read.
>>>
>>> Signed-off-by: Zou Nan hai <nanhai.zou at intel.com>
>>
>>Please start sending your changes out for review so we don't have to do
>>review after the fact.
>>
>>g0.2 is "reserved, delivered as zeroes".  What does this commit fix?
>>Also, in the first hunk we immediately write m0.2 with an offset after
>>your 0 write.
>>
>>>  src/mesa/drivers/dri/i965/brw_eu_emit.c |    9 +++++++++
>>>  1 files changed, 9 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>> index 57313a5..c5cde22 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>> @@ -1759,6 +1759,11 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
>>>     brw_set_compression_control(p, BRW_COMPRESSION_NONE);
>>>     brw_set_mask_control(p, BRW_MASK_DISABLE);
>>>     brw_set_predicate_control(p, BRW_PREDICATE_NONE);
>>> +
>>> +   /* M0.2 is global offset */
>>> +   brw_MOV(p, retype(get_element(brw_message_reg(0), 2),
>>BRW_REGISTER_TYPE_D),
>>> +                   brw_imm_d(0));
>>> +
>>>     brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr,
>>2),
>>>  		     BRW_REGISTER_TYPE_UD),
>>>  	   brw_imm_ud(location));
>>> @@ -1809,6 +1814,10 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
>>>     brw_set_mask_control(p, BRW_MASK_DISABLE);
>>>     brw_set_predicate_control(p, BRW_PREDICATE_NONE);
>>>
>>> +   /* M0.2 is global offset */
>>> +   brw_MOV(p, retype(get_element(brw_message_reg(0), 2),
>>BRW_REGISTER_TYPE_D),
>>> +                   brw_imm_d(0));
>>> +
>>>     /* M1.0 is block offset 0, M1.4 is block offset 1, all other
>>>      * fields ignored.
>>>      */
>>>
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