[Mesa-dev] [PATCH 7/8] intel: Stop creating the wrapped stencil irb.
Eric Anholt
eric at anholt.net
Thu Dec 8 13:40:02 PST 2011
There were only two places it was really used at this point, which was
in the batchbuffer emit of the separate stencil packets for gen6/7.
Just write in the ->stencil_mt reference in those two places and ditch
all this flailing around with allocation and refcounts.
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 40 +++++++++------
src/mesa/drivers/dri/i965/gen7_misc_state.c | 11 +++-
src/mesa/drivers/dri/intel/intel_fbo.c | 64 ++++++++----------------
src/mesa/drivers/dri/intel/intel_fbo.h | 6 --
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 3 +-
5 files changed, 54 insertions(+), 70 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 8a6ee70..39876f8 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -208,6 +208,7 @@ brw_depthbuffer_format(struct brw_context *brw)
if (!drb &&
(srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) &&
+ !srb->mt->stencil_mt &&
srb->Base.Format == MESA_FORMAT_S8_Z24) {
drb = srb;
}
@@ -236,8 +237,10 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ struct intel_mipmap_tree *stencil_mt = NULL;
struct intel_region *hiz_region = NULL;
unsigned int len;
+ bool separate_stencil = false;
if (depth_irb &&
depth_irb->mt &&
@@ -253,17 +256,21 @@ static void emit_depthbuffer(struct brw_context *brw)
intel_emit_depth_stall_flushes(intel);
}
- /*
- * If either depth or stencil buffer has packed depth/stencil format,
- * then don't use separate stencil. Emit only a depth buffer.
+ /* Find the real separate stencil mt if present. */
+ if (stencil_irb) {
+ stencil_mt = stencil_irb->mt;
+ if (stencil_mt->stencil_mt)
+ stencil_mt = stencil_mt->stencil_mt;
+
+ if (stencil_mt->format == MESA_FORMAT_S8)
+ separate_stencil = true;
+ }
+
+ /* If there's a packed depth/stencil bound to stencil only, we need to
+ * emit the packed depth/stencil buffer packet.
*/
- if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
- stencil_irb = NULL;
- } else if (!depth_irb && stencil_irb
- && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
+ if (!depth_irb && stencil_irb && !separate_stencil)
depth_irb = stencil_irb;
- stencil_irb = NULL;
- }
if (intel->gen >= 6)
len = 7;
@@ -272,7 +279,7 @@ static void emit_depthbuffer(struct brw_context *brw)
else
len = 5;
- if (!depth_irb && !stencil_irb) {
+ if (!depth_irb && !separate_stencil) {
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
@@ -289,7 +296,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
- } else if (!depth_irb && stencil_irb) {
+ } else if (!depth_irb && separate_stencil) {
/*
* There exists a separate stencil buffer but no depth buffer.
*
@@ -314,10 +321,9 @@ static void emit_depthbuffer(struct brw_context *brw)
* Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
* [DevGT+]: This field must be set to TRUE.
*/
- struct intel_region *region = stencil_irb->mt->region;
+ struct intel_region *region = stencil_mt->region;
assert(intel->has_separate_stencil);
- assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
@@ -343,7 +349,7 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t tile_x, tile_y, offset;
/* If using separate stencil, hiz must be enabled. */
- assert(!stencil_irb || hiz_region);
+ assert(!separate_stencil || hiz_region);
offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
@@ -378,7 +384,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
}
- if (hiz_region || stencil_irb) {
+ if (hiz_region || separate_stencil) {
/*
* In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
* stencil enable' and 'hiz enable' bits were set. Therefore we must
@@ -405,8 +411,8 @@ static void emit_depthbuffer(struct brw_context *brw)
}
/* Emit stencil buffer. */
- if (stencil_irb) {
- struct intel_region *region = stencil_irb->mt->region;
+ if (separate_stencil) {
+ struct intel_region *region = stencil_mt->region;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(region->pitch * region->cpp - 1);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index c50cd30..94bd598 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -111,10 +111,17 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ struct intel_mipmap_tree *stencil_mt = srb->mt;
+
+ if (stencil_mt->stencil_mt)
+ stencil_mt = stencil_mt->stencil_mt;
+
+ assert(stencil_mt->format == MESA_FORMAT_S8);
+
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
- OUT_BATCH(srb->mt->region->pitch * srb->mt->region->cpp - 1);
- OUT_RELOC(srb->mt->region->bo,
+ OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1);
+ OUT_RELOC(stencil_mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index a5b779b..28ed43a 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -81,9 +81,12 @@ struct intel_region*
intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex)
{
struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, attIndex);
- if (irb && irb->mt)
- return irb->mt->region;
- else
+ if (irb && irb->mt) {
+ if (attIndex == BUFFER_STENCIL && irb->mt->stencil_mt)
+ return irb->mt->stencil_mt->region;
+ else
+ return irb->mt->region;
+ } else
return NULL;
}
@@ -111,7 +114,6 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
intel_miptree_release(&irb->mt);
_mesa_reference_renderbuffer(&irb->wrapped_depth, NULL);
- _mesa_reference_renderbuffer(&irb->wrapped_stencil, NULL);
free(irb);
}
@@ -260,24 +262,19 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
if (irb->mt->stencil_mt) {
bool ok;
- struct intel_renderbuffer *depth_irb, *stencil_irb;
+ struct intel_renderbuffer *depth_irb;
/* The RB got allocated as separate stencil. Hook up our wrapped
- * renderbuffers so that consumers of intel_get_renderbuffer() end up
- * with pointers to the separate pieces.
+ * renderbuffer so that consumers of intel_get_renderbuffer(BUFFER_DEPTH)
+ * end up with pointers to the separate depth.
*/
if (!irb->wrapped_depth) {
_mesa_reference_renderbuffer(&irb->wrapped_depth,
intel_new_renderbuffer(ctx, ~0));
}
- if (!irb->wrapped_stencil) {
- _mesa_reference_renderbuffer(&irb->wrapped_stencil,
- intel_new_renderbuffer(ctx, ~0));
- }
depth_irb = intel_renderbuffer(irb->wrapped_depth);
- stencil_irb = intel_renderbuffer(irb->wrapped_stencil);
- if (!depth_irb || !stencil_irb) {
+ if (!depth_irb) {
intel_miptree_release(&irb->mt);
return false;
}
@@ -288,13 +285,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
MESA_FORMAT_X8_Z24,
GL_DEPTH_COMPONENT24);
assert(ok);
-
- ok = intel_renderbuffer_update_wrapper(intel, stencil_irb,
- irb->mt->stencil_mt,
- 0, 0, /* level, layer */
- MESA_FORMAT_S8,
- GL_STENCIL_INDEX);
- assert(ok);
}
return true;
@@ -541,32 +531,25 @@ intel_renderbuffer_update_wrapper(struct intel_context *intel,
irb->mt_level = level;
irb->mt_layer = layer;
+ intel_miptree_reference(&irb->mt, mt);
if (mt->stencil_mt && _mesa_is_depthstencil_format(rb->InternalFormat)) {
- assert((irb->wrapped_depth == NULL) == (irb->wrapped_stencil == NULL));
-
struct intel_renderbuffer *depth_irb;
- struct intel_renderbuffer *stencil_irb;
if (!irb->wrapped_depth) {
depth_irb = intel_renderbuffer_wrap_miptree(intel,
mt, level, layer,
MESA_FORMAT_X8_Z24,
GL_DEPTH_COMPONENT24);
- stencil_irb = intel_renderbuffer_wrap_miptree(intel,
- mt->stencil_mt,
- level, layer,
- MESA_FORMAT_S8,
- GL_STENCIL_INDEX8);
_mesa_reference_renderbuffer(&irb->wrapped_depth, &depth_irb->Base);
- _mesa_reference_renderbuffer(&irb->wrapped_stencil, &stencil_irb->Base);
- if (!irb->wrapped_depth || !irb->wrapped_stencil)
+ if (!irb->wrapped_depth) {
+ intel_miptree_release(&irb->mt);
return false;
+ }
} else {
bool ok = true;
depth_irb = intel_renderbuffer(irb->wrapped_depth);
- stencil_irb = intel_renderbuffer(irb->wrapped_stencil);
ok &= intel_renderbuffer_update_wrapper(intel,
depth_irb,
@@ -574,20 +557,12 @@ intel_renderbuffer_update_wrapper(struct intel_context *intel,
level, layer,
MESA_FORMAT_X8_Z24,
GL_DEPTH_COMPONENT24);
- ok &= intel_renderbuffer_update_wrapper(intel,
- stencil_irb,
- mt->stencil_mt,
- level, layer,
- MESA_FORMAT_S8,
- GL_STENCIL_INDEX8);
- if (!ok)
+ if (!ok) {
+ intel_miptree_release(&irb->mt);
return false;
+ }
}
-
- intel_miptree_reference(&depth_irb->mt->stencil_mt, stencil_irb->mt);
- intel_miptree_reference(&irb->mt, depth_irb->mt);
} else {
- intel_miptree_reference(&irb->mt, mt);
intel_renderbuffer_set_draw_offset(irb);
if (mt->hiz_mt == NULL &&
@@ -857,8 +832,11 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
if (depthRb)
depth_mt = depthRb->mt;
- if (stencilRb)
+ if (stencilRb) {
stencil_mt = stencilRb->mt;
+ if (stencil_mt->stencil_mt)
+ stencil_mt = stencil_mt->stencil_mt;
+ }
if (depth_mt && stencil_mt) {
if (depth_mt == stencil_mt) {
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 174e1c2..b8dbb34 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -72,7 +72,6 @@ struct intel_renderbuffer
* are the real renderbuffers.
*/
struct gl_renderbuffer *wrapped_depth;
- struct gl_renderbuffer *wrapped_stencil;
/** \} */
GLuint draw_x, draw_y; /**< Offset of drawing within the region */
@@ -134,11 +133,6 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, gl_buffer_index attIndex)
irb = intel_renderbuffer(irb->wrapped_depth);
}
break;
- case BUFFER_STENCIL:
- if (irb->wrapped_stencil) {
- irb = intel_renderbuffer(irb->wrapped_stencil);
- }
- break;
default:
break;
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index c24fa8e..fef1dcf 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -149,8 +149,7 @@ struct intel_mipmap_tree
* two miptrees for storing the data. If the depthstencil texture or rb is
* MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
* MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
- * MESA_FORMAT_S8_Z24 (textures) or MESA_FORMAT_X8_Z24 (renderbuffers).
- * mt->stencil_mt->format will always be MESA_FORMAT_S8.
+ * MESA_FORMAT_S8_Z24.
*/
gl_format format;
--
1.7.7.3
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