[Mesa-dev] [PATCH 7/8] i965 gen6+: Make intel_batchbuffer_emit_mi_flush() actually flush.

[Kenneth Graunke]

On 12/14/2011 08:28 AM, Paul Berry wrote:
> On 14 December 2011 02:59, Kenneth Graunke <kenneth at whitecape.org
> <mailto:kenneth at whitecape.org>> wrote:
> 
>     On 12/13/2011 03:35 PM, Paul Berry wrote:
>     > Previous to this patch, the function intel_batchbuffer_emit_mi_flush()
>     > was a bit of a misnomer.  On Gen4+, when not using the blit engine, it
>     > didn't actually flush the pipeline--it simply generated a
>     > _3DSTATE_PIPE_CONTROL command with the necessary bits set to flush GPU
> 
>     It's actually just called "PIPE_CONTROL", never 3DSTATE_PIPE_CONTROL.
> 
> 
> (Checks the docs).  Hmm, you're right.  For some reason we call it
> _3DSTATE_PIPE_CONTROL in our #defines (see intel_reg.h).  Still, it
> seems better for the commit message to match the documentation.  I'll
> change the commit message.

We also call it CMD_PIPE_CONTROL (see brw_defines.h).  Nice, huh?

I'm always hugely skeptical of intel_reg.h because it contains a lot of
i8xx and i915 defines that sometimes have similar names to i965 stuff
but isn't the same.

In this case, _3DSTATE_PIPE_CONTROL == CMD_PIPE_CONTROL | 2 (i.e. with
length included).  Not a huge fan of including the length in the #define
either.

But I'm digressing :)