[Mesa-dev] [PATCH] i965: Don't use BRW_DEPTHFORMAT_D24_UNORM_X8_UINT on Gen4.

[Eric Anholt]

On Tue, 20 Dec 2011 23:30:29 -0800, Kenneth Graunke <kenneth at whitecape.org> wrote:
> X8 depth formats weren't supported until Ironlake (Gen 5).
> 
> Fixes GPU hangs introduced in d84a180417d1eabd680554970f1eaaa93abcd41e.
> One example test case was "fbo-missing-attachment-blit from".
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c |    4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
> 
> I tested this by comparing full piglit runs on GM45 between d84a180417d~1
> and d84a180417d with this patch applied on top of it.  No changes, no hangs.
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 8a6ee70..21885a6 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -218,7 +218,9 @@ brw_depthbuffer_format(struct brw_context *brw)
>     case MESA_FORMAT_Z32_FLOAT:
>        return BRW_DEPTHFORMAT_D32_FLOAT;
>     case MESA_FORMAT_X8_Z24:
> -      return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
> +      if (intel->gen >= 5)
> +	 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
> +      /* Gen4 doesn't support X8; use S8 instead. */
>     case MESA_FORMAT_S8_Z24:
>        return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
>     default:

Oh, thanks!  I think an explicit else case would be nicer to read than
an implicit fallthrough, though.
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