[Mesa-dev] [PATCH 4/5] radeon: Convert to use GLbitfield64 directly.
Mathias Fröhlich
Mathias.Froehlich at gmx.net
Mon Dec 26 01:29:16 PST 2011
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
---
src/mesa/drivers/dri/r200/r200_swtcl.c | 35 +++++++++---------
.../drivers/dri/radeon/radeon_common_context.h | 2 +-
src/mesa/drivers/dri/radeon/radeon_swtcl.c | 38
++++++++++----------
3 files changed, 37 insertions(+), 38 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c
b/src/mesa/drivers/dri/r200/r200_swtcl.c
index 303d3fb..25bae21 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -80,13 +80,11 @@ static void r200SetVertexFormat( struct gl_context *ctx )
r200ContextPtr rmesa = R200_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
- DECLARE_RENDERINPUTS(index_bitset);
+ GLbitfield64 index_bitset = tnl->render_inputs_bitset;
int fmt_0 = 0;
int fmt_1 = 0;
int offset = 0;
- RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
-
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
@@ -103,7 +101,8 @@ static void r200SetVertexFormat( struct gl_context *ctx )
* build up a hardware vertex.
*/
if ( !rmesa->swtcl.needproj ||
- RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX
)) { /* need w coord for projected textures */
+ (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) ) {
+ /* need w coord for projected textures */
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F, R200_VTX_XY | R200_VTX_Z0 |
R200_VTX_W0 );
offset = 4;
}
@@ -112,7 +111,7 @@ static void r200SetVertexFormat( struct gl_context *ctx )
offset = 3;
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POINTSIZE )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE)) {
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, R200_VTX_POINT_SIZE );
offset += 1;
}
@@ -126,11 +125,11 @@ static void r200SetVertexFormat( struct gl_context *ctx
)
offset += 1;
rmesa->swtcl.specoffset = 0;
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
- RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset &
+ (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) |
BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
#if MESA_LITTLE_ENDIAN
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, (R200_VTX_PK_RGBA <<
R200_VTX_COLOR_1_SHIFT) );
}
@@ -138,21 +137,21 @@ static void r200SetVertexFormat( struct gl_context *ctx
)
EMIT_PAD( 3 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, (R200_VTX_PK_RGBA <<
R200_VTX_COLOR_1_SHIFT) );
}
else {
EMIT_PAD( 1 );
}
#else
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, (R200_VTX_PK_RGBA <<
R200_VTX_COLOR_1_SHIFT) );
}
else {
EMIT_PAD( 1 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, (R200_VTX_PK_RGBA <<
R200_VTX_COLOR_1_SHIFT) );
}
@@ -162,11 +161,11 @@ static void r200SetVertexFormat( struct gl_context *ctx
)
#endif
}
- if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX
)) {
+ if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
int i;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
fmt_1 |= sz << (3 * i);
@@ -182,7 +181,7 @@ static void r200SetVertexFormat( struct gl_context *ctx )
rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_SPEC_ALPHA;
}
- if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
+ if (rmesa->radeon.tnl_index_bitset != index_bitset ||
(rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) ||
(rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) {
R200_NEWPRIM(rmesa);
@@ -196,7 +195,7 @@ static void r200SetVertexFormat( struct gl_context *ctx )
rmesa->radeon.swtcl.vertex_attr_count,
NULL, 0 );
rmesa->radeon.swtcl.vertex_size /= 4;
- RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
+ rmesa->radeon.tnl_index_bitset = index_bitset;
}
}
@@ -254,12 +253,12 @@ void r200ChooseVertexState( struct gl_context *ctx )
/* HW perspective divide is a win, but tiny vertex formats are a
* bigger one.
*/
- if (!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX,
_TNL_LAST_TEX )
+ if ((0 == (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0,
_TNL_NUM_TEX)))
|| (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
rmesa->swtcl.needproj = GL_TRUE;
vte |= R200_VTX_XY_FMT | R200_VTX_Z_FMT;
vte &= ~R200_VTX_W0_FMT;
- if (RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX,
_TNL_LAST_TEX )) {
+ if (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0,
_TNL_NUM_TEX)) {
vap &= ~R200_VAP_FORCE_W_TO_ONE;
}
else {
@@ -717,7 +716,7 @@ void r200Fallback( struct gl_context *ctx, GLuint bit,
GLboolean mode )
*/
_tnl_invalidate_vertex_state( ctx, ~0 );
_tnl_invalidate_vertices( ctx, ~0 );
- RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
+ rmesa->radeon.tnl_index_bitset = 0;
r200ChooseVertexState( ctx );
r200ChooseRenderState( ctx );
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h
b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 5a32079..1fa7547 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -412,7 +412,7 @@ struct radeon_context {
GLuint TclFallback;
GLuint Fallback;
GLuint NewGLState;
- DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last
tnl_install_attrs */
+ GLbitfield64 tnl_index_bitset; /* index of bits for last
tnl_install_attrs */
/* Drawable information */
unsigned int lastStamp;
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index 3cda09d..4f264a6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -92,12 +92,10 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
r100ContextPtr rmesa = R100_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
- DECLARE_RENDERINPUTS(index_bitset);
+ GLbitfield64 index_bitset = tnl->render_inputs_bitset;
int fmt_0 = 0;
int offset = 0;
- RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
-
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
@@ -114,7 +112,8 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
* build up a hardware vertex.
*/
if ( !rmesa->swtcl.needproj ||
- RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX
)) { /* for projtex */
+ (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
+ /* for projtex */
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z |
RADEON_CP_VC_FRMT_W0 );
offset = 4;
@@ -136,11 +135,11 @@ static void radeonSetVertexFormat( struct gl_context
*ctx )
offset += 1;
rmesa->swtcl.specoffset = 0;
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
- RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset &
+ (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) |
BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
#if MESA_LITTLE_ENDIAN
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
RADEON_CP_VC_FRMT_PKSPEC );
@@ -149,7 +148,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
EMIT_PAD( 3 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
@@ -157,7 +156,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
EMIT_PAD( 1 );
}
#else
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
@@ -165,7 +164,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
EMIT_PAD( 1 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
RADEON_CP_VC_FRMT_PKSPEC );
@@ -176,11 +175,11 @@ static void radeonSetVertexFormat( struct gl_context
*ctx )
#endif
}
- if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX
)) {
+ if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
int i;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
switch (sz) {
@@ -214,8 +213,8 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
}
}
- if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
- fmt_0 != rmesa->swtcl.vertex_format) {
+ if (rmesa->radeon.tnl_index_bitset != index_bitset ||
+ fmt_0 != rmesa->swtcl.vertex_format) {
RADEON_NEWPRIM(rmesa);
rmesa->swtcl.vertex_format = fmt_0;
rmesa->radeon.swtcl.vertex_size =
@@ -224,7 +223,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx
)
rmesa->radeon.swtcl.vertex_attr_count,
NULL, 0 );
rmesa->radeon.swtcl.vertex_size /= 4;
- RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
+ rmesa->radeon.tnl_index_bitset = index_bitset;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
"%s: vertex_size= %d floats\n", __FUNCTION__, rmesa-
>radeon.swtcl.vertex_size);
}
@@ -290,9 +289,10 @@ void radeonChooseVertexState( struct gl_context *ctx )
* bigger one.
*/
- if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX,
_TNL_LAST_TEX ) &&
- !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
- || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
+ if ((0 == (tnl->render_inputs_bitset &
+ (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
+ | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
+ || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
rmesa->swtcl.needproj = GL_TRUE;
se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
@@ -824,7 +824,7 @@ void radeonFallback( struct gl_context *ctx, GLuint bit,
GLboolean mode )
*/
_tnl_invalidate_vertex_state( ctx, ~0 );
_tnl_invalidate_vertices( ctx, ~0 );
- RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
+ rmesa->radeon.tnl_index_bitset = 0;
radeonChooseVertexState( ctx );
radeonChooseRenderState( ctx );
}
--
1.7.4.4
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