[Mesa-dev] [PATCH] i965: fix timer query on gen6+

[Eric Anholt]

On Mon, 18 Jul 2011 09:19:32 +0800, "Zou, Nanhai" <nanhai.zou at intel.com> wrote:
> >>-----Original Message-----
> >>From: Eric Anholt [mailto:eric at anholt.net]
> >>Sent: 2011年7月17日 8:08
> >>To: Zou, Nanhai; mesa-dev at lists.freedesktop.org
> >>Subject: Re: [Mesa-dev] [PATCH] i965: fix timer query on gen6+
> >>
> >>On Fri, 15 Jul 2011 18:07:51 +0800, Zou Nan hai <nanhai.zou at intel.com> wrote:
> >>>  	on gen6+, PIPE_CONTROL reported timestamp counter is a
> >>>  	64 bits value, toggles every 80 ns
> >>
> >>> @@ -58,7 +58,10 @@ brw_queryobj_get_results(struct brw_query_object *query)
> >>>     drm_intel_bo_map(query->bo, GL_FALSE);
> >>>     results = query->bo->virtual;
> >>>     if (query->Base.Target == GL_TIME_ELAPSED_EXT) {
> >>> -      query->Base.Result += 1000 * ((results[1] >> 32) - (results[0] >>
> >>32));
> >>> +	if (gen >= 6)
> >>> +		query->Base.Result += 80 * (results[1]  - results[0]);
> >>> +	else
> >>> +		query->Base.Result += 1000 * ((results[1] >> 32) - (results[0] >>
> >>32));
> >>
> >>You've mangled the whitespace here.  Also, bits 32:63 appear to be
> >>reserved and should be ignored.
> 
> 	I can't find that information in bspec. Bspec says it is a 64 bit value.

Oh, wait, it's MBZ.  Sorry.  From the Sandybridge PRM, Vol1 Part3, page 73:

"63:36 Reserved Project: All Format: MBZ

 35:0 Timestamp Value          Project:    All   Format: U32
     This register toggles every 80 ns of time."

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