[Mesa-dev] [PATCH 00/12] i965: Begin implementing HiZ
Chad Versace
chad at chad-versace.us
Mon May 2 13:14:47 PDT 2011
I'm NAK'ing this patchset. I'm removing the context-global hiz
enablement field (intel_context.use_hiz) and making hiz enablement a
property of individual renderbuffers.
On 04/29/2011 06:04 PM, chad at chad-versace.us wrote:
> From: Chad Versace <chad.versace at intel.com>
>
> Begin implementing HiZ for Gen >= 5. Since it's incomplete, the patch series
> leaves HiZ disabled default. But you can force enable it with env
> INTEL_USE_HIZ=1.
>
> I did a full Piglit run on Gen 5 and found no regressions.
>
> These patches live on my personal hiz branch.
>
>
> What doesn't work
> -----------------
> * Rendering to a window framebuffer with depth or stencil attachment.
> * Rendering to an FBO with GL_DEPTH_STENCIL_ATTACHMENT.
> * HiZ/depth resolves.
>
> What does work
> --------------
> * Rendering to an FBO with GL_DEPTH_ATTACHMENT and no GL_STENCIL_ATTACHMENT.
> * Rendering to an FBO with GL_DEPTH_ATTACHMENT and GL_STENCIL_ATTACHMENT.
>
> Chad Versace (12):
> intel: Add flag intel_context.use_hiz
> intel: Override intel_context.use_hiz with env var INTEL_USE_HIZ
> intel: Change supported texture formats
> mesa/main: Add MESA_FORMAT_X8_Z24 to _mesa_choose_tex_format
> intel: Add HiZ region to intel_renderbuffer
> intel: Change allocation of user-created renderbuffers for HiZ
> i965: Change FBO completeness criteria when HiZ is enabled
> i965: Refactor prepare_depthbuffer() and emit_depthbuffer()
> i965: Emit 3D_STATE_HIER_DEPTH_BUFFER
> i965: Define tracked state for separate stencil buffer
> intel: Change signature of intel_context.vtbl.set_draw_region
> i965: Update cached stencil region pointer when updating draw buffers
>
> src/mesa/drivers/dri/i915/i915_vtbl.c | 3 +
> src/mesa/drivers/dri/i965/brw_context.h | 5 +
> src/mesa/drivers/dri/i965/brw_misc_state.c | 118 ++++++++++++++++++----
> src/mesa/drivers/dri/i965/brw_state.h | 1 +
> src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +
> src/mesa/drivers/dri/i965/brw_vtbl.c | 10 ++
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +-
> src/mesa/drivers/dri/intel/intel_buffers.c | 28 +++--
> src/mesa/drivers/dri/intel/intel_context.c | 34 ++++++-
> src/mesa/drivers/dri/intel/intel_context.h | 2 +
> src/mesa/drivers/dri/intel/intel_fbo.c | 76 +++++++++++---
> src/mesa/drivers/dri/intel/intel_fbo.h | 20 ++++
> src/mesa/drivers/dri/intel/intel_span.c | 1 +
> src/mesa/drivers/dri/intel/intel_tex_format.c | 1 +
> src/mesa/main/texformat.c | 2 +
> 15 files changed, 258 insertions(+), 48 deletions(-)
>
--
Chad Versace
chad at chad-versace.us
More information about the mesa-dev
mailing list