No subject

Wed May 18 14:13:20 PDT 2011

about to find a sweet spot btw number of instruction, number of
register, instruction scheduling. This sweet spot is not always the
minimum number of instruction/register.

With the idea i described my aim is to minimize the impact of CPU &
scheduling, rendering thousand of tri from a vbo with destination
being the biggest fbo and disabling all interfering pipeline (zbuffer,
blending, ...) should produce result once averaged over run that are
dependant primarily on the shader execution time.


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