No subject

came about on accident.  Gen4-5 had separate READ/WRITE data port SFIDs,
while Gen6+ have separate SFIDs for each cache.  It turns out that the
Gen6 Sampler Cache and Gen4-5 READ data port both had SFID 4.  The
original code apparently tried to preserve the notion of read/write
data ports until later cleanups labeled it properly as Sampler Cache.

NOTE: This is a candidate for the 7.11 branch.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_eu_emit.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

Eric seemed to think that using the sampler cache was intentional.  Reading
through git log/git blame leads me to believe that it was an accident...

We may decide to leave the existing behavior, but I'd at least like to see it
commented.

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index bcd640e..6775ce2 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -624,13 +624,6 @@ brw_set_dp_read_message(struct brw_compile *p,
       insn->bits3.gen7_dp.end_of_thread = 0;
       insn->header.destreg__conditionalmod = GEN7_MESSAGE_TARGET_DP_DATA_CACHE;
    } else if (intel->gen == 6) {
-      uint32_t target_function;
-
-      if (target_cache == BRW_DATAPORT_READ_TARGET_DATA_CACHE)
-	 target_function = GEN6_MESSAGE_TARGET_DP_SAMPLER_CACHE;
-      else
-	 target_function = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
-
       insn->bits3.gen6_dp.binding_table_index = binding_table_index;
       insn->bits3.gen6_dp.msg_control = msg_control;
       insn->bits3.gen6_dp.pixel_scoreboard_clear = 0;
@@ -640,7 +633,7 @@ brw_set_dp_read_message(struct brw_compile *p,
       insn->bits3.gen6_dp.response_length = response_length;
       insn->bits3.gen6_dp.msg_length = msg_length;
       insn->bits3.gen6_dp.end_of_thread = 0;
-      insn->header.destreg__conditionalmod = target_function;
+      insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
    } else if (intel->gen == 5) {
       insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
       insn->bits3.dp_read_gen5.msg_control = msg_control;
-- 
1.7.7