[Mesa-dev] [PATCH 5/5] intel: Replace intel_renderbuffer::region with a miptree
Chad Versace
chad at chad-versace.us
Thu Oct 27 18:55:51 PDT 2011
This is in preparation for 1) fixing the implementation of
glFramebufferTexture(GL_DEPTH_STENCIL) for separate stencil and
2) supporting HiZ for miptrees. As a nice benefit, this lays down some
preliminary groundwork for easily texturing from any renderbuffer, even
those of the window system.
Without this patch, it is indeed possible to implement the above, but the
code would be more difficult to work with.
In addition, intel_mipmap_tree::hiz_region will also be replaced with
a miptree by a future commit.
No Piglit regressions on gen6.
Signed-off-by: Chad Versace <chad at chad-versace.us>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 29 +++++---
src/mesa/drivers/dri/i965/brw_vtbl.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +--
src/mesa/drivers/dri/i965/gen7_misc_state.c | 15 ++--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +-
src/mesa/drivers/dri/intel/intel_blit.c | 21 ++++--
src/mesa/drivers/dri/intel/intel_buffer_objects.c | 8 +-
src/mesa/drivers/dri/intel/intel_buffers.c | 9 ++-
src/mesa/drivers/dri/intel/intel_context.c | 55 ++++++++++-----
src/mesa/drivers/dri/intel/intel_fbo.c | 80 ++++++++++----------
src/mesa/drivers/dri/intel/intel_fbo.h | 6 +-
src/mesa/drivers/dri/intel/intel_pixel_copy.c | 5 +-
src/mesa/drivers/dri/intel/intel_screen.c | 3 +-
src/mesa/drivers/dri/intel/intel_span.c | 30 +++++----
src/mesa/drivers/dri/intel/intel_tex_copy.c | 14 +++--
src/mesa/drivers/dri/intel/intel_tex_image.c | 6 +-
16 files changed, 170 insertions(+), 128 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 2e6780b..908feb8 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -33,6 +33,7 @@
#include "intel_batchbuffer.h"
#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#include "brw_context.h"
@@ -205,11 +206,11 @@ static void prepare_depthbuffer(struct brw_context *brw)
struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
if (drb)
- brw_add_validated_bo(brw, drb->region->bo);
- if (drb && drb->hiz_region)
- brw_add_validated_bo(brw, drb->hiz_region->bo);
+ brw_add_validated_bo(brw, drb->mt->region->bo);
+ if (drb && drb->mt->hiz_region)
+ brw_add_validated_bo(brw, drb->mt->hiz_region->bo);
if (srb)
- brw_add_validated_bo(brw, srb->region->bo);
+ brw_add_validated_bo(brw, srb->mt->region->bo);
}
static void emit_depthbuffer(struct brw_context *brw)
@@ -220,9 +221,14 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
+ struct intel_region *hiz_region = NULL;
unsigned int len;
+ if (depth_irb &&
+ depth_irb->mt) {
+ hiz_region = depth_irb->mt->hiz_region;
+ }
+
/* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
* non-pipelined state that will need the PIPE_CONTROL workaround.
*/
@@ -288,6 +294,8 @@ static void emit_depthbuffer(struct brw_context *brw)
* [DevGT]: This field must be set to the same value (enabled or
* disabled) as Hierarchical Depth Buffer Enable
*/
+ struct intel_region *region = stencil_irb->mt->region;
+
assert(intel->has_separate_stencil);
assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
@@ -299,8 +307,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(BRW_TILEWALK_YMAJOR << 26) |
(BRW_SURFACE_2D << 29));
OUT_BATCH(0);
- OUT_BATCH(((stencil_irb->region->width - 1) << 6) |
- (2 * stencil_irb->region->height - 1) << 19);
+ OUT_BATCH(((region->width - 1) << 6) |
+ (2 * region->height - 1) << 19);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -310,7 +318,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
} else {
- struct intel_region *region = depth_irb->region;
+ struct intel_region *region = depth_irb->mt->region;
unsigned int format;
uint32_t tile_x, tile_y, offset;
@@ -395,10 +403,11 @@ static void emit_depthbuffer(struct brw_context *brw)
/* Emit stencil buffer. */
if (stencil_irb) {
+ struct intel_region *region = stencil_irb->mt->region;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
- OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
- OUT_RELOC(stencil_irb->region->bo,
+ OUT_BATCH(region->pitch * region->cpp - 1);
+ OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 52be175..8d280a8 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -147,7 +147,7 @@ brw_update_draw_buffer(struct intel_context *intel)
/* Check some stencil invariants. These should probably be in
* emit_depthbuffer().
*/
- if (irbStencil && irbStencil->region) {
+ if (irbStencil && irbStencil->mt) {
if (!intel->has_separate_stencil)
assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
if (fb_has_hiz || intel->must_use_separate_stencil)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 355e23d..1e86d5c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -447,7 +447,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- struct intel_region *region = irb->region;
+ struct intel_region *region = irb->mt->region;
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
@@ -551,10 +551,8 @@ prepare_wm_surfaces(struct brw_context *brw)
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- struct intel_region *region = irb ? irb->region : NULL;
-
- if (region)
- brw_add_validated_bo(brw, region->bo);
+ if (irb && irb->mt)
+ brw_add_validated_bo(brw, irb->mt->region->bo);
nr_surfaces = SURF_INDEX_DRAW(i) + 1;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index e160641..abf1655 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -22,6 +22,7 @@
*/
#include "intel_batchbuffer.h"
+#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#include "intel_fbo.h"
#include "brw_context.h"
@@ -38,7 +39,7 @@ gen7_depth_format(struct brw_context *brw)
struct intel_region *region = NULL;
if (drb)
- region = drb->region;
+ region = drb->mt->region;
else
return BRW_DEPTHFORMAT_D32_FLOAT;
@@ -65,9 +66,9 @@ static void prepare_depthbuffer(struct brw_context *brw)
struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
if (drb)
- brw_add_validated_bo(brw, drb->region->bo);
+ brw_add_validated_bo(brw, drb->mt->region->bo);
if (srb)
- brw_add_validated_bo(brw, srb->region->bo);
+ brw_add_validated_bo(brw, srb->mt->region->bo);
}
static void emit_depthbuffer(struct brw_context *brw)
@@ -92,7 +93,7 @@ static void emit_depthbuffer(struct brw_context *brw)
if (srb == NULL) {
dw1 |= (BRW_SURFACE_NULL << 29);
} else {
- struct intel_region *region = srb->region;
+ struct intel_region *region = srb->mt->region;
/* _NEW_STENCIL: enable stencil buffer writes */
dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
@@ -112,7 +113,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- struct intel_region *region = drb->region;
+ struct intel_region *region = drb->mt->region;
uint32_t tile_x, tile_y, offset;
offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
@@ -154,8 +155,8 @@ static void emit_depthbuffer(struct brw_context *brw)
} else {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
- OUT_BATCH(srb->region->pitch * srb->region->cpp - 1);
- OUT_RELOC(srb->region->bo,
+ OUT_BATCH(srb->mt->region->pitch * srb->mt->region->cpp - 1);
+ OUT_RELOC(srb->mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index d2b9866..f29234b 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -234,7 +234,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- struct intel_region *region = irb->region;
+ struct intel_region *region = irb->mt->region;
struct gen7_surface_state *surf;
uint32_t tile_x, tile_y;
@@ -313,10 +313,9 @@ prepare_wm_surfaces(struct brw_context *brw)
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- struct intel_region *region = irb ? irb->region : NULL;
- if (region)
- brw_add_validated_bo(brw, region->bo);
+ if (irb && irb->mt)
+ brw_add_validated_bo(brw, irb->mt->region->bo);
nr_surfaces = SURF_INDEX_DRAW(i) + 1;
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index def226c..6051548 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -261,13 +261,18 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
int x1, y1, x2, y2;
uint32_t clear_val;
uint32_t BR13, CMD;
+ struct intel_region *region;
int pitch, cpp;
drm_intel_bo *aper_array[2];
mask &= ~(1 << buf);
irb = intel_get_renderbuffer(fb, buf);
- if (irb == NULL || irb->region == NULL || irb->region->bo == NULL) {
+ if (irb && irb->mt) {
+ region = irb->mt->region;
+ assert(region);
+ assert(region->bo);
+ } else {
fail_mask |= 1 << buf;
continue;
}
@@ -278,12 +283,12 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
x2 = cx + cw + irb->draw_x;
y2 = cy + ch + irb->draw_y;
- pitch = irb->region->pitch;
- cpp = irb->region->cpp;
+ pitch = region->pitch;
+ cpp = region->cpp;
DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
__FUNCTION__,
- irb->region->bo, (pitch * cpp),
+ region->bo, (pitch * cpp),
x1, y1, x2 - x1, y2 - y1);
BR13 = 0xf0 << 16;
@@ -299,10 +304,10 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
}
}
- assert(irb->region->tiling != I915_TILING_Y);
+ assert(region->tiling != I915_TILING_Y);
#ifndef I915
- if (irb->region->tiling != I915_TILING_NONE) {
+ if (region->tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
pitch /= 4;
}
@@ -351,7 +356,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
/* do space check before going any further */
aper_array[0] = intel->batch.bo;
- aper_array[1] = irb->region->bo;
+ aper_array[1] = region->bo;
if (drm_intel_bufmgr_check_aperture_space(aper_array,
ARRAY_SIZE(aper_array)) != 0) {
@@ -363,7 +368,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
OUT_BATCH(BR13);
OUT_BATCH((y1 << 16) | x1);
OUT_BATCH((y2 << 16) | x2);
- OUT_RELOC_FENCED(irb->region->bo,
+ OUT_RELOC_FENCED(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH(clear_val);
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 75d95b1..4a1a816 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -766,10 +766,10 @@ intel_render_object_purgeable(struct gl_context * ctx,
(void) option;
intel = intel_renderbuffer(obj);
- if (intel->region == NULL)
+ if (intel->mt == NULL)
return GL_RELEASED_APPLE;
- return intel_buffer_purgeable(intel->region->bo);
+ return intel_buffer_purgeable(intel->mt->region->bo);
}
static GLenum
@@ -823,10 +823,10 @@ intel_render_object_unpurgeable(struct gl_context * ctx,
(void) option;
intel = intel_renderbuffer(obj);
- if (intel->region == NULL)
+ if (intel->mt == NULL)
return GL_UNDEFINED_APPLE;
- return intel_buffer_unpurgeable(intel->region->bo);
+ return intel_buffer_unpurgeable(intel->mt->region->bo);
}
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index 08f5c4d..4632751 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -28,6 +28,7 @@
#include "intel_context.h"
#include "intel_buffers.h"
#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
#include "main/framebuffer.h"
#include "main/renderbuffer.h"
@@ -40,8 +41,8 @@ intel_drawbuf_region(struct intel_context *intel)
{
struct intel_renderbuffer *irbColor =
intel_renderbuffer(intel->ctx.DrawBuffer->_ColorDrawBuffers[0]);
- if (irbColor)
- return irbColor->region;
+ if (irbColor && irbColor->mt)
+ return irbColor->mt->region;
else
return NULL;
}
@@ -54,8 +55,8 @@ intel_readbuf_region(struct intel_context *intel)
{
struct intel_renderbuffer *irb
= intel_renderbuffer(intel->ctx.ReadBuffer->_ColorReadBuffer);
- if (irb)
- return irb->region;
+ if (irb && irb->mt)
+ return irb->mt->region;
else
return NULL;
}
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 501b00d..309889a 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -53,6 +53,7 @@
#include "intel_fbo.h"
#include "intel_bufmgr.h"
#include "intel_screen.h"
+#include "intel_mipmap_tree.h"
#include "drirenderbuffer.h"
#include "utils.h"
@@ -1127,7 +1128,9 @@ intel_process_dri2_buffer_no_separate_stencil(struct intel_context *intel,
if (!rb)
return;
- if (rb->region && rb->region->name == buffer->name)
+ if (rb->mt &&
+ rb->mt->region &&
+ rb->mt->region->name == buffer->name)
return;
if (unlikely(INTEL_DEBUG & DEBUG_DRI)) {
@@ -1141,23 +1144,33 @@ intel_process_dri2_buffer_no_separate_stencil(struct intel_context *intel,
if (buffer->attachment == __DRI_BUFFER_STENCIL) {
struct intel_renderbuffer *depth_rb =
intel_get_renderbuffer(fb, BUFFER_DEPTH);
- identify_depth_and_stencil = depth_rb && depth_rb->region;
+ identify_depth_and_stencil = depth_rb && depth_rb->mt;
}
if (identify_depth_and_stencil) {
if (unlikely(INTEL_DEBUG & DEBUG_DRI)) {
fprintf(stderr, "(reusing depth buffer as stencil)\n");
}
- intel_region_reference(&rb->region, depth_rb->region);
+ intel_miptree_reference(&rb->mt, depth_rb->mt);
} else {
- intel_region_release(&rb->region);
- rb->region = intel_region_alloc_for_handle(intel->intelScreen,
+ intel_miptree_release(&rb->mt);
+ struct intel_region *region =
+ intel_region_alloc_for_handle(intel->intelScreen,
buffer->cpp,
drawable->w,
drawable->h,
buffer->pitch / buffer->cpp,
buffer->name,
buffer_name);
+ if (!region)
+ return;
+ rb->mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb->Base.Format,
+ region);
+ intel_region_release(®ion);
+ if (!rb->mt)
+ return;
}
if (buffer->attachment == __DRI_BUFFER_DEPTH_STENCIL) {
@@ -1170,7 +1183,7 @@ intel_process_dri2_buffer_no_separate_stencil(struct intel_context *intel,
/* The rb passed in is the BUFFER_DEPTH attachment, and we need
* to associate this region to BUFFER_STENCIL as well.
*/
- intel_region_reference(&stencil_rb->region, rb->region);
+ intel_miptree_reference(&stencil_rb->mt, rb->mt);
}
}
@@ -1312,11 +1325,13 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
/* If the renderbuffer's and DRIbuffer's regions match, then continue. */
if ((buffer->attachment != __DRI_BUFFER_HIZ &&
- rb->region &&
- rb->region->name == buffer->name) ||
+ rb->mt &&
+ rb->mt->region &&
+ rb->mt->region->name == buffer->name) ||
(buffer->attachment == __DRI_BUFFER_HIZ &&
- rb->hiz_region &&
- rb->hiz_region->name == buffer->name)) {
+ rb->mt &&
+ rb->mt->hiz_region &&
+ rb->mt->hiz_region->name == buffer->name)) {
return;
}
@@ -1354,9 +1369,12 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
buffer_name);
if (buffer->attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(&rb->hiz_region, region);
+ intel_region_reference(&rb->mt->hiz_region, region);
} else {
- intel_region_reference(&rb->region, region);
+ rb->mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb->Base.Format,
+ region);;
}
intel_region_release(®ion);
@@ -1436,7 +1454,7 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
assert(stencil_rb->Base.Format == MESA_FORMAT_S8);
assert(depth_rb && depth_rb->Base.Format == MESA_FORMAT_X8_Z24);
- if (stencil_rb->region->tiling == I915_TILING_NONE) {
+ if (stencil_rb->mt->region->tiling == I915_TILING_NONE) {
/*
* The stencil buffer is actually W tiled. The region's tiling is
* I915_TILING_NONE, however, because the GTT is incapable of W
@@ -1517,11 +1535,14 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
/ depth_stencil_buffer->cpp,
depth_stencil_buffer->name,
"dri2 depth / stencil buffer");
- intel_region_reference(&intel_get_renderbuffer(fb, BUFFER_DEPTH)->region,
- region);
- intel_region_reference(&intel_get_renderbuffer(fb, BUFFER_STENCIL)->region,
- region);
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ depth_stencil_rb->Base.Format,
+ region);
intel_region_release(®ion);
+ intel_miptree_reference(&intel_get_renderbuffer(fb, BUFFER_DEPTH)->mt, mt);
+ intel_miptree_reference(&intel_get_renderbuffer(fb, BUFFER_STENCIL)->mt, mt);
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index d870e25..5997d3b 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -59,15 +59,15 @@ intel_framebuffer_has_hiz(struct gl_framebuffer *fb)
struct intel_renderbuffer *rb = NULL;
if (fb)
rb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- return rb && rb->hiz_region;
+ return rb && rb->mt && rb->mt->hiz_region;
}
struct intel_region*
intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex)
{
struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, attIndex);
- if (irb)
- return irb->region;
+ if (irb && irb->mt)
+ return irb->mt->region;
else
return NULL;
}
@@ -93,8 +93,7 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
ASSERT(irb);
- intel_region_release(&irb->region);
- intel_region_release(&irb->hiz_region);
+ intel_miptree_release(&irb->mt);
_mesa_reference_renderbuffer(&irb->wrapped_depth, NULL);
_mesa_reference_renderbuffer(&irb->wrapped_stencil, NULL);
@@ -165,13 +164,7 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
intel_flush(ctx);
- /* free old region */
- if (irb->region) {
- intel_region_release(&irb->region);
- }
- if (irb->hiz_region) {
- intel_region_release(&irb->hiz_region);
- }
+ intel_miptree_release(&irb->mt);
/* allocate new memory region/renderbuffer */
@@ -204,14 +197,15 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
*
* If we neglect to double the pitch, then render corruption occurs.
*/
- irb->region = intel_region_alloc(intel->intelScreen,
- I915_TILING_NONE,
- cpp * 2,
- ALIGN(width, 64),
- ALIGN((height + 1) / 2, 64),
- true);
- if (!irb->region)
- return false;
+ irb->mt = intel_miptree_create_for_renderbuffer(
+ intel,
+ rb->Format,
+ I915_TILING_NONE,
+ cpp * 2,
+ ALIGN(width, 64),
+ ALIGN((height + 1) / 2, 64));
+ if (!irb->mt)
+ return false;
} else if (irb->Base.Format == MESA_FORMAT_S8_Z24
&& intel->must_use_separate_stencil) {
@@ -248,20 +242,21 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
_mesa_reference_renderbuffer(&irb->wrapped_stencil, stencil_rb);
} else {
- irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
- width, height, true);
- if (!irb->region)
+ irb->mt = intel_miptree_create_for_renderbuffer(intel, rb->Format,
+ tiling, cpp,
+ width, height);
+ if (!irb->mt)
return false;
if (intel->vtbl.is_hiz_depth_format(intel, rb->Format)) {
- irb->hiz_region = intel_region_alloc(intel->intelScreen,
- I915_TILING_Y,
- irb->region->cpp,
- irb->region->width,
- irb->region->height,
- true);
- if (!irb->hiz_region) {
- intel_region_release(&irb->region);
+ irb->mt->hiz_region = intel_region_alloc(intel->intelScreen,
+ I915_TILING_Y,
+ cpp,
+ rb->Width,
+ rb->Height,
+ true);
+ if (!irb->mt->hiz_region) {
+ intel_miptree_release(&irb->mt);
return false;
}
}
@@ -300,7 +295,12 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
}
irb = intel_renderbuffer(rb);
- intel_region_reference(&irb->region, image->region);
+ irb->mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ image->format,
+ image->region);
+ if (!irb->mt)
+ return;
rb->InternalFormat = image->internal_format;
rb->Width = image->region->width;
@@ -528,9 +528,8 @@ intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
_mesa_reference_renderbuffer(&irb->wrapped_stencil,
intel_image->stencil_rb);
} else {
- intel_region_reference(&irb->region, intel_image->mt->region);
+ intel_miptree_reference(&irb->mt, intel_image->mt);
}
-
return true;
}
@@ -596,20 +595,21 @@ intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb,
uint32_t *tile_x,
uint32_t *tile_y)
{
- int cpp = irb->region->cpp;
- uint32_t pitch = irb->region->pitch * cpp;
+ struct intel_region *region = irb->mt->region;
+ int cpp = region->cpp;
+ uint32_t pitch = region->pitch * cpp;
- if (irb->region->tiling == I915_TILING_NONE) {
+ if (region->tiling == I915_TILING_NONE) {
*tile_x = 0;
*tile_y = 0;
return irb->draw_x * cpp + irb->draw_y * pitch;
- } else if (irb->region->tiling == I915_TILING_X) {
+ } else if (region->tiling == I915_TILING_X) {
*tile_x = irb->draw_x % (512 / cpp);
*tile_y = irb->draw_y % 8;
return ((irb->draw_y / 8) * (8 * pitch) +
(irb->draw_x - *tile_x) / (512 / cpp) * 4096);
} else {
- assert(irb->region->tiling == I915_TILING_Y);
+ assert(region->tiling == I915_TILING_Y);
*tile_x = irb->draw_x % (128 / cpp);
*tile_y = irb->draw_y % 32;
return ((irb->draw_y / 32) * (32 * pitch) +
@@ -710,7 +710,7 @@ intel_render_texture(struct gl_context * ctx,
intel_miptree_copy_teximage(intel, intel_image, new_mt);
intel_renderbuffer_set_draw_offset(irb, intel_image, att->Zoffset);
- intel_region_reference(&irb->region, intel_image->mt->region);
+ intel_miptree_reference(&irb->mt, intel_image->mt);
intel_miptree_release(&new_mt);
}
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 8fb4393..80f7c80 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -35,6 +35,7 @@
#include "intel_screen.h"
struct intel_context;
+struct intel_mipmap_tree;
struct intel_texture_image;
/**
@@ -43,10 +44,7 @@ struct intel_texture_image;
struct intel_renderbuffer
{
struct gl_renderbuffer Base;
- struct intel_region *region;
-
- /** Only used by depth renderbuffers for which HiZ is enabled. */
- struct intel_region *hiz_region;
+ struct intel_mipmap_tree *mt;
/**
* \name Packed depth/stencil unwrappers
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
index 89d5c51..2682e15 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
@@ -34,6 +34,7 @@
#include "intel_context.h"
#include "intel_buffers.h"
+#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#include "intel_pixel.h"
#include "intel_fbo.h"
@@ -188,8 +189,8 @@ do_blit_copypixels(struct gl_context * ctx,
dsty += draw_irb->draw_y;
if (!intel_region_copy(intel,
- draw_irb->region, 0, dstx, dsty,
- read_irb->region, 0, srcx, srcy,
+ draw_irb->mt->region, 0, dstx, dsty,
+ read_irb->mt->region, 0, srcx, srcy,
width, height, flip,
ctx->Color.ColorLogicOpEnabled ?
ctx->Color.LogicOp : GL_COPY)) {
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 6a6b851..2470ecc 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -86,6 +86,7 @@ const GLuint __driNConfigOptions = 11;
#include "intel_bufmgr.h"
#include "intel_chipset.h"
#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
#include "intel_screen.h"
#include "intel_tex.h"
#include "intel_regions.h"
@@ -201,7 +202,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
image->format = rb->Format;
image->data_type = rb->DataType;
image->data = loaderPrivate;
- intel_region_reference(&image->region, irb->region);
+ intel_region_reference(&image->region, irb->mt->region);
return image;
}
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index bdc4a0e..5706bc1 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -39,6 +39,7 @@
#include "intel_buffers.h"
#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
#include "intel_screen.h"
#include "intel_span.h"
#include "intel_regions.h"
@@ -58,7 +59,7 @@ intel_set_span_functions(struct intel_context *intel,
int minx = 0, miny = 0; \
int maxx = rb->Width; \
int maxy = rb->Height; \
- int pitch = rb->RowStride * irb->region->cpp; \
+ int pitch = rb->RowStride * irb->mt->region->cpp; \
void *buf = rb->Data; \
GLuint p; \
(void) p;
@@ -139,9 +140,9 @@ intel_set_span_functions(struct intel_context *intel,
* required. \
*/ \
struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
- uint8_t *buf = irb->region->bo->virtual; \
- unsigned stride = irb->region->pitch; \
- unsigned height = 2 * irb->region->height; \
+ uint8_t *buf = irb->mt->region->bo->virtual; \
+ unsigned stride = irb->mt->region->pitch; \
+ unsigned height = 2 * irb->mt->region->height; \
bool flip = rb->Name == 0; \
int y_scale = flip ? -1 : 1; \
int y_bias = flip ? (height - 1) : 0; \
@@ -222,6 +223,7 @@ void
intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
{
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+ struct intel_region *region;
if (!irb)
return;
@@ -231,24 +233,26 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
if (irb->wrapped_stencil)
intel_renderbuffer_map(intel, irb->wrapped_stencil);
- if (!irb->region)
+ if (irb->mt)
+ region = irb->mt->region;
+ else
return;
- drm_intel_gem_bo_map_gtt(irb->region->bo);
+ drm_intel_gem_bo_map_gtt(region->bo);
- rb->Data = irb->region->bo->virtual;
- rb->RowStride = irb->region->pitch;
+ rb->Data = region->bo->virtual;
+ rb->RowStride = region->pitch;
if (!rb->Name) {
/* Flip orientation of the window system buffer */
- rb->Data += rb->RowStride * (irb->region->height - 1) * irb->region->cpp;
+ rb->Data += rb->RowStride * (region->height - 1) * region->cpp;
rb->RowStride = -rb->RowStride;
} else {
/* Adjust the base pointer of a texture image drawbuffer to the image
* within the miptree region (all else has draw_x/y = 0).
*/
- rb->Data += irb->draw_x * irb->region->cpp;
- rb->Data += irb->draw_y * rb->RowStride * irb->region->cpp;
+ rb->Data += irb->draw_x * region->cpp;
+ rb->Data += irb->draw_y * rb->RowStride * region->cpp;
}
intel_set_span_functions(intel, rb);
@@ -268,10 +272,10 @@ intel_renderbuffer_unmap(struct intel_context *intel,
if (irb->wrapped_stencil)
intel_renderbuffer_unmap(intel, irb->wrapped_stencil);
- if (!irb->region)
+ if (!irb->mt)
return;
- drm_intel_gem_bo_unmap_gtt(irb->region->bo);
+ drm_intel_gem_bo_unmap_gtt(irb->mt->region->bo);
rb->GetRow = NULL;
rb->PutRow = NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 2df4ef6..543326a 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -71,6 +71,7 @@ intel_copy_texsubimage(struct intel_context *intel,
{
struct gl_context *ctx = &intel->ctx;
struct intel_renderbuffer *irb;
+ struct intel_region *region;
const GLenum internalFormat = intelImage->base.Base.InternalFormat;
bool copy_supported = false;
bool copy_supported_with_alpha_override = false;
@@ -78,11 +79,14 @@ intel_copy_texsubimage(struct intel_context *intel,
intel_prepare_render(intel);
irb = get_teximage_readbuffer(intel, internalFormat);
- if (!intelImage->mt || !irb || !irb->region) {
+ if (!intelImage->mt || !irb || !irb->mt) {
if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS))
fprintf(stderr, "%s fail %p %p (0x%08x)\n",
__FUNCTION__, intelImage->mt, irb, internalFormat);
return false;
+ } else {
+ region = irb->mt->region;
+ assert(region);
}
copy_supported = intelImage->base.Base.TexFormat == irb->Base.Format;
@@ -127,19 +131,19 @@ intel_copy_texsubimage(struct intel_context *intel,
if (ctx->ReadBuffer->Name == 0) {
/* Flip vertical orientation for system framebuffers */
y = ctx->ReadBuffer->Height - (y + height);
- src_pitch = -irb->region->pitch;
+ src_pitch = -region->pitch;
} else {
/* reading from a FBO, y is already oriented the way we like */
- src_pitch = irb->region->pitch;
+ src_pitch = region->pitch;
}
/* blit from src buffer to texture */
if (!intelEmitCopyBlit(intel,
intelImage->mt->cpp,
src_pitch,
- irb->region->bo,
+ region->bo,
0,
- irb->region->tiling,
+ region->tiling,
intelImage->mt->region->pitch,
intelImage->mt->region->bo,
0,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index eaf034a..0ba1b17 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -306,7 +306,7 @@ intel_tex_image_s8z24_create_renderbuffers(struct intel_context *intel,
idrb = intel_renderbuffer(drb);
isrb = intel_renderbuffer(srb);
- intel_region_reference(&idrb->region, image->mt->region);
+ intel_miptree_reference(&idrb->mt, image->mt);
ok = intel_alloc_renderbuffer_storage(ctx, srb, GL_STENCIL_INDEX8,
width, height);
@@ -466,7 +466,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
/* If the region isn't set, then intel_update_renderbuffers was unable
* to get the buffers for the drawable.
*/
- if (rb->region == NULL)
+ if (!rb || !rb->mt)
return;
if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
@@ -480,7 +480,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
_mesa_lock_texture(&intel->ctx, texObj);
texImage = _mesa_get_tex_image(ctx, texObj, target, level);
- intel_set_texture_image_region(ctx, texImage, rb->region, target,
+ intel_set_texture_image_region(ctx, texImage, rb->mt->region, target,
internalFormat, texFormat);
_mesa_unlock_texture(&intel->ctx, texObj);
}
--
1.7.6.4
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