[Mesa-dev] [PATCH] i965: fix the constant interp bitmask for flat mode

[Yuanhan Liu]

Fix the constant interpolation enable bit mask for flat light mode.
FRAG_BIT_COL0 attribute bit might be 0, in which case we need to
shift one more bit right.

This would fix the oglc specularColor test fail on both Sandybridge and
Ivybridge.

v2: move the constant interp bitmask setup code into for(; attr <
FRAG_ATTRIB_MAX; attr++) loop suggested by Eric.

Signed-off-by: Yuanhan Liu <yuanhan.liu at linux.intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
---
 src/mesa/drivers/dri/i965/gen6_sf_state.c |   19 +++++++++++++------
 src/mesa/drivers/dri/i965/gen7_sf_state.c |   19 +++++++++++++------
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 5bb731d..cc9bdf4 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -231,12 +231,6 @@ upload_sf_state(struct brw_context *brw)
 	 (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
    }
 
-   /* flat shading */
-   if (ctx->Light.ShadeModel == GL_FLAT) {
-       dw17 |= ((brw->fragment_program->Base.InputsRead & (FRAG_BIT_COL0 | FRAG_BIT_COL1)) >>
-                ((brw->fragment_program->Base.InputsRead & FRAG_BIT_WPOS) ? 0 : 1));
-   }
-
    /* Create the mapping from the FS inputs we produce to the VS outputs
     * they source from.
     */
@@ -254,6 +248,19 @@ upload_sf_state(struct brw_context *brw)
       if (attr == FRAG_ATTRIB_PNTC)
 	 dw16 |= (1 << input_index);
 
+      /* flat shading */
+      if (ctx->Light.ShadeModel == GL_FLAT) {
+         /*
+          * Setup the Constant Interpolation Enable bit mask for each
+          * corresponding attribute(currently, we only care two attrs:
+          * FRAG_BIT_COL0 and FRAG_BIT_COL1).
+          *
+          * FIXME: should we care other attributes?
+          */
+	  if (attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1)
+             dw17 |= (1 << input_index);
+      }
+
       /* The hardware can only do the overrides on 16 overrides at a
        * time, and the other up to 16 have to be lined up so that the
        * input index = the output index.  We'll need to do some
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 0f97cea..6910e02 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -58,13 +58,7 @@ upload_sbe_state(struct brw_context *brw)
       dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
 
    dw10 = 0;
-
-   /* _NEW_LIGHT (flat shading) */
    dw11 = 0;
-   if (ctx->Light.ShadeModel == GL_FLAT) {
-       dw11 |= ((brw->fragment_program->Base.InputsRead & (FRAG_BIT_COL0 | FRAG_BIT_COL1)) >>
-                ((brw->fragment_program->Base.InputsRead & FRAG_BIT_WPOS) ? 0 : 1));
-   }
 
    /* Create the mapping from the FS inputs we produce to the VS outputs
     * they source from.
@@ -82,6 +76,19 @@ upload_sbe_state(struct brw_context *brw)
       if (attr == FRAG_ATTRIB_PNTC)
 	 dw10 |= (1 << input_index);
 
+      /* flat shading */
+      if (ctx->Light.ShadeModel == GL_FLAT) {
+         /*
+          * Setup the Constant Interpolation Enable bit mask for each
+          * corresponding attribute(currently, we only care two attrs:
+          * FRAG_BIT_COL0 and FRAG_BIT_COL1).
+          *
+          * FIXME: should we care other attributes?
+          */
+	  if (attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1)
+             dw11 |= (1 << input_index);
+      }
+
       /* The hardware can only do the overrides on 16 overrides at a
        * time, and the other up to 16 have to be lined up so that the
        * input index = the output index.  We'll need to do some
-- 
1.7.4.4