[Mesa-dev] [PATCH 6/8] i965/vs: Use proper register type for MATH instruction GRF temporaries.

[Kenneth Graunke]

The MATH instruction unfortunately only operates on GRF registers with
an HStride of 1, so we often need to create a temporary GRF.  For
integer division and modulus, we need to use an integer register.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 4ae9f14..4c7e336 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -326,10 +326,12 @@ vec4_visitor::emit_math2_gen6(enum opcode opcode,
     */
 
    expanded = src_reg(this, glsl_type::vec4_type);
+   expanded.type = src0.type;
    emit(MOV(dst_reg(expanded), src0));
    src0 = expanded;
 
    expanded = src_reg(this, glsl_type::vec4_type);
+   expanded.type = src1.type;
    emit(MOV(dst_reg(expanded), src1));
    src1 = expanded;
 
@@ -338,6 +340,7 @@ vec4_visitor::emit_math2_gen6(enum opcode opcode,
        * writemasks.
        */
       dst_reg temp_dst = dst_reg(this, glsl_type::vec4_type);
+      temp_dst.type = src0.type;
 
       emit(opcode, temp_dst, src0, src1);
 
-- 
1.7.6.1