[Mesa-dev] [PATCH 2/8] i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants.

[Eric Anholt]

On Wed,  7 Sep 2011 07:39:11 -0700, Kenneth Graunke <kenneth at whitecape.org> wrote:
> This mirrors the structure Eric used in the new VS backend, and seems
> simpler.  In particular, the math1/math2 split will avoid having to
> figure out how many operands there are, as this is already known by the
> caller.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp      |    3 +-
>  src/mesa/drivers/dri/i965/brw_fs.h        |   15 +++-
>  src/mesa/drivers/dri/i965/brw_fs_emit.cpp |  142 ++++++++++++++++++-----------
>  3 files changed, 104 insertions(+), 56 deletions(-)
> 
> Tested on Sandybridge and Ironlake.
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 7f5194b..83737bc 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -597,8 +597,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
>  
>        inst = emit(opcode, dst, src0, src1);
>     } else {
> -      emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1);
> -      inst = emit(opcode, dst, src0, reg_null_f);
> +      inst = emit(opcode, dst, src0, src1);

I'd rather see us keep the MRF write at this level.  It means you get to
compute into the MRF instead of emitting an extra mov next to the SEND.
(I was going to say that if you do make this change, you need to update
implied_mrf_writes() for POW, but it turns out we incorrectly say "2"
for that currently).
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