[Mesa-dev] [PATCH] intel: Remove intel_renderbuffer::hiz_region
Chad Versace
chad at chad-versace.us
Fri Sep 23 19:10:40 PDT 2011
And replace it with intel_renderbuffer::region::hiz::region.
v2: In intel_process_dri2_buffer*(), don't call intel_get_renderbuffer() to
get the depthbuffer. The variable 'rb' already points to it.
v3: Actually do what I intended in the v2 change (oops). Replace depth_irb
with rb.
Signed-off-by: Chad Versace <chad at chad-versace.us>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 27 +++++++++++----------
src/mesa/drivers/dri/intel/intel_context.c | 10 +++++--
src/mesa/drivers/dri/intel/intel_fbo.c | 36 ++++++---------------------
src/mesa/drivers/dri/intel/intel_fbo.h | 3 --
4 files changed, 29 insertions(+), 47 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index ce4fc84..5adf2d7 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -206,8 +206,8 @@ static void prepare_depthbuffer(struct brw_context *brw)
if (drb)
brw_add_validated_bo(brw, drb->region->buffer);
- if (drb && drb->hiz_region)
- brw_add_validated_bo(brw, drb->hiz_region->buffer);
+ if (drb && drb->region->hiz.region)
+ brw_add_validated_bo(brw, drb->region->hiz.region->buffer);
if (srb)
brw_add_validated_bo(brw, srb->region->buffer);
}
@@ -220,7 +220,7 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
+ bool has_hiz = intel_framebuffer_has_hiz(fb);
unsigned int len;
/* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
@@ -313,7 +313,7 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t tile_x, tile_y, offset;
/* If using separate stencil, hiz must be enabled. */
- assert(!stencil_irb || hiz_region);
+ assert(!stencil_irb || has_hiz);
switch (region->cpp) {
case 2:
@@ -322,7 +322,7 @@ static void emit_depthbuffer(struct brw_context *brw)
case 4:
if (intel->depth_buffer_is_float)
format = BRW_DEPTHFORMAT_D32_FLOAT;
- else if (hiz_region)
+ else if (has_hiz)
format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
else
format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
@@ -335,14 +335,14 @@ static void emit_depthbuffer(struct brw_context *brw)
offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
- assert(!hiz_region || region->tiling == I915_TILING_Y);
+ assert(!has_hiz || region->tiling == I915_TILING_Y);
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
- ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
- ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
+ ((has_hiz ? 1 : 0) << 21) | /* separate stencil enable */
+ ((has_hiz ? 1 : 0) << 22) | /* hiz enable */
(BRW_TILEWALK_YMAJOR << 26) |
((region->tiling != I915_TILING_NONE) << 27) |
(BRW_SURFACE_2D << 29));
@@ -365,7 +365,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
}
- if (hiz_region || stencil_irb) {
+ if (has_hiz || stencil_irb) {
/*
* In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
* stencil enable' and 'hiz enable' bits were set. Therefore we must
@@ -375,11 +375,12 @@ static void emit_depthbuffer(struct brw_context *brw)
*/
/* Emit hiz buffer. */
- if (hiz_region) {
+ if (has_hiz) {
+ struct intel_hiz_control *hiz = &depth_irb->region->hiz;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
- OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
- OUT_RELOC(hiz_region->buffer,
+ OUT_BATCH(hiz->region->pitch * hiz->region->cpp - 1);
+ OUT_RELOC(hiz->region->buffer,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
@@ -417,7 +418,7 @@ static void emit_depthbuffer(struct brw_context *brw)
* 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
* when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
*/
- if (intel->gen >= 6 || hiz_region) {
+ if (intel->gen >= 6 || has_hiz) {
if (intel->gen == 6)
intel_emit_post_sync_nonzero_flush(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index caac24a..3f66ae1 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1318,8 +1318,8 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
rb->region &&
rb->region->name == buffer->name) ||
(buffer->attachment == __DRI_BUFFER_HIZ &&
- rb->hiz_region &&
- rb->hiz_region->name == buffer->name)) {
+ rb->region->hiz.region &&
+ rb->region->hiz.region->name == buffer->name)) {
return;
}
@@ -1357,7 +1357,11 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
buffer_name);
if (buffer->attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(&rb->hiz_region, region);
+ /* We assume that the depth buffer has already been processed. */
+ struct intel_hiz_control *hiz = &rb->region->hiz;
+ intel_region_reference(&hiz->region, region);
+ hiz->need_resolve = INTEL_HIZ_NEED_NO_RESOLVE;
+ hiz->depth_format = rb->Base.Format;
} else {
intel_region_reference(&rb->region, region);
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index bf57e30..9b22aa4 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -75,7 +75,6 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
ASSERT(irb);
intel_region_release(&irb->region);
- intel_region_release(&irb->hiz_region);
_mesa_reference_renderbuffer(&irb->wrapped_depth, NULL);
_mesa_reference_renderbuffer(&irb->wrapped_stencil, NULL);
@@ -104,8 +103,8 @@ intel_framebuffer_get_hiz_region(struct gl_framebuffer *fb)
if (fb)
rb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- if (rb)
- return rb->hiz_region;
+ if (rb && rb->region)
+ return rb->region->hiz.region;
else
return NULL;
}
@@ -183,9 +182,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
if (irb->region) {
intel_region_release(&irb->region);
}
- if (irb->hiz_region) {
- intel_region_release(&irb->hiz_region);
- }
/* allocate new memory region/renderbuffer */
@@ -268,13 +264,8 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
return false;
if (intel->vtbl.is_hiz_depth_format(intel, rb->Format)) {
- irb->hiz_region = intel_region_alloc(intel->intelScreen,
- I915_TILING_Y,
- irb->region->cpp,
- irb->region->width,
- irb->region->height,
- GL_TRUE);
- if (!irb->hiz_region) {
+ bool ok = intel_renderbuffer_alloc_hiz(intel, irb);
+ if (!ok) {
intel_region_release(&irb->region);
return false;
}
@@ -585,21 +576,10 @@ intel_update_tex_wrapper_regions(struct intel_context *intel,
/* Allocate the texture's hiz region if necessary. */
if (intel->vtbl.is_hiz_depth_format(intel, rb->Format)
- && !intel_image->mt->hiz_region) {
- intel_image->mt->hiz_region =
- intel_region_alloc(intel->intelScreen,
- I915_TILING_Y,
- _mesa_get_format_bytes(rb->Format),
- rb->Width,
- rb->Height,
- GL_TRUE);
- if (!intel_image->mt->hiz_region)
- return GL_FALSE;
- }
-
- /* Point the renderbuffer's hiz region to the texture's hiz region. */
- if (irb->hiz_region != intel_image->mt->hiz_region) {
- intel_region_reference(&irb->hiz_region, intel_image->mt->hiz_region);
+ && irb->region->hiz.region == NULL) {
+ bool ok = intel_renderbuffer_alloc_hiz(intel, irb);
+ if (!ok)
+ return false;
}
return GL_TRUE;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 377cb1b..6573d40 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -45,9 +45,6 @@ struct intel_renderbuffer
struct gl_renderbuffer Base;
struct intel_region *region;
- /** Only used by depth renderbuffers for which HiZ is enabled. */
- struct intel_region *hiz_region;
-
/**
* \name Packed depth/stencil unwrappers
*
--
1.7.6.2
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