[Mesa-dev] [PATCH 1/2] radeonsi: Handle TGSI DIV opcode.

[Tom Stellard]

On Thu, Aug 02, 2012 at 05:37:02PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
> 
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> ---
>  src/gallium/drivers/radeon/SIInstructions.td |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
> index 94748b6..31b9e5e 100644
> --- a/src/gallium/drivers/radeon/SIInstructions.td
> +++ b/src/gallium/drivers/radeon/SIInstructions.td
> @@ -1088,6 +1088,11 @@ def : Pat <
>  /* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
>  def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
>  
> +def : Pat <
> +  (int_AMDGPU_div AllReg_32:$src0, AllReg_32:$src1),
> +  (V_MUL_LEGACY_F32_e32 AllReg_32:$src0, (V_RCP_LEGACY_F32_e32 AllReg_32:$src1))
> +>;
> +
>  /********** ================== **********/
>  /**********   VOP3 Patterns    **********/
>  /********** ================== **********/
> -- 
> 1.7.10.4
> 
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