[Mesa-dev] [PATCH v2] i965: Rework the extra flushes surrounding occlusion queries.

[Kenneth Graunke]

This removes the CS stall on Ivybridge.

On Sandybridge, the depth stall needs to be preceded by a non-zero
post-sync op, which requires a CS stall, which needs a stall at
scoreboard.  Emit the full workaround.

Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_queryobj.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

v2: Keep depth count write and depth stall together.  Do the full
    post-sync non-zero workaround.  This seems much safer to me.

Daniel: the irony, of course, is that the part you objected to came
from the first patch in your series... :)

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 1e03d08..b39f644 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -91,14 +91,11 @@ static void
 write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
 {
    if (intel->gen >= 6) {
-      BEGIN_BATCH(9);
-
-      /* workaround: CS stall required before depth stall. */
-      OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
-      OUT_BATCH(PIPE_CONTROL_CS_STALL);
-      OUT_BATCH(0); /* write address */
-      OUT_BATCH(0); /* write data */
+      /* Emit Sandybridge workaround flush: */
+      if (intel->gen == 6)
+         intel_emit_post_sync_nonzero_flush(intel);
 
+      BEGIN_BATCH(5);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
       OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
                 PIPE_CONTROL_WRITE_DEPTH_COUNT);
-- 
1.7.11.4