[Mesa-dev] [PATCH 1/5] radeon/llvm: add support to fetch temps as vectors

[Alex Deucher]

On Mon, Aug 13, 2012 at 7:29 AM, Christian König
<deathsimple at vodafone.de> wrote:
> Necessary for texture fetches with temp regs as source on SI.
>
> Signed-off-by: Christian König <deathsimple at vodafone.de>

For the series:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../drivers/radeon/radeon_setup_tgsi_llvm.c        |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
> index 641d277..04469e2 100644
> --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
> +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
> @@ -159,11 +159,21 @@ emit_fetch_temporary(
>  {
>         struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
>         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
> +       if (swizzle == ~0) {
> +               LLVMValueRef values[TGSI_NUM_CHANNELS] = {};
> +               unsigned chan;
> +               for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
> +                       values[chan] = emit_fetch_temporary(bld_base, reg, type, chan);
> +               }
> +               return lp_build_gather_values(bld_base->base.gallivm, values,
> +                                               TGSI_NUM_CHANNELS);
> +       }
> +
>         if (reg->Register.Indirect) {
>                 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
>                 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->temps_array, &array_index,
>                                                 1, "");
> -       return LLVMBuildLoad(builder, ptr, "");
> +               return LLVMBuildLoad(builder, ptr, "");
>         } else {
>                 LLVMValueRef temp_ptr;
>                 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
> --
> 1.7.9.5
>
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