[Mesa-dev] [PATCH 1/2] radeon/llvm: Basic support for SI EXEC register.

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
 src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp |    3 +++
 src/gallium/drivers/radeon/SIGenRegisterInfo.pl |    7 +++++++
 src/gallium/drivers/radeon/SIInstructions.td    |   15 +++++++++++++--
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp
index 1f36105..eeb8d26 100644
--- a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp
@@ -81,6 +81,9 @@ void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
           VCCUsed = true;
           continue;
         }
+        if (reg == AMDGPU::EXEC) {
+          continue;
+        }
         if (AMDGPU::SReg_32RegClass.contains(reg)) {
           isSGPR = true;
           width = 1;
diff --git a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
index 110c04f..dd0efcc 100644
--- a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
+++ b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
@@ -88,6 +88,7 @@ class SGPR_256 <bits<8> num, string name, list<Register> subregs> :
     SI_256 <name, subregs>;
 
 def VCC : SIReg<"VCC">;
+def EXEC : SIReg<"EXEC">;
 def SCC : SIReg<"SCC">;
 def SREG_LIT_0 : SIReg <"S LIT 0">;
 
@@ -169,6 +170,7 @@ def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 
 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
+def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
 
 STRING
 
@@ -271,6 +273,11 @@ sub print_reg_class {
     push (@registers, 'VCC')
   }
 
+  #Add EXEC to SReg_64
+  if ($class_prefix eq 'SReg' and $reg_width == 64) {
+    push (@registers, 'EXEC')
+  }
+
   my $reg_list = join(', ', @registers);
 
   print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n  (add $reg_list)\n>{\n";
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 3047321..ee4c8f5 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -630,8 +630,19 @@ def S_CBRANCH_VCCNZ : SOPP <
   "S_CBRANCH_VCCNZ",
   []
 >;
-//def S_CBRANCH_EXECZ : SOPP_ <0x00000008, "S_CBRANCH_EXECZ", []>;
-//def S_CBRANCH_EXECNZ : SOPP_ <0x00000009, "S_CBRANCH_EXECNZ", []>;
+
+let DisableEncoding = "$exec" in {
+def S_CBRANCH_EXECZ : SOPP <
+  0x00000008, (ins brtarget:$target, EXECReg:$exec),
+  "S_CBRANCH_EXECZ",
+  []
+>;
+def S_CBRANCH_EXECNZ : SOPP <
+  0x00000009, (ins brtarget:$target, EXECReg:$exec),
+  "S_CBRANCH_EXECNZ",
+  []
+>;
+} // End DisableEncoding = "$exec"
 
 
 } // End isBranch = 1
-- 
1.7.10.4